| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 99 v16i64 = 49, // 16 x i64 enumerator
267 SimpleTy == MVT::v16i64); in is1024BitVector()
346 case v16i64: in getVectorElementType()
386 case v16i64: in getVectorNumElements()
500 case v16i64: return 1024; in getSizeInBits()
630 if (NumElements == 16) return MVT::v16i64; in getVectorVT()
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| D | ValueTypes.td | 76 def v16i64 : ValueType<1024,49>; // 16 x i64 vector value
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 176 case MVT::v16i64: return "v16i64"; in getEVTString()
254 case MVT::v16i64: return VectorType::get(Type::getInt64Ty(Context), 16); in getTypeForEVT()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
416 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
546 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
885 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
1089 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1097 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1573 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1579 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
[all …]
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| D | HexagonRegisterInfo.td | 221 [v128i8, v64i16, v32i32, v16i64], 1024,
225 [v128i8, v64i16, v32i32, v16i64], 1024,
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| D | HexagonIntrinsicsV60.td | 137 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
138 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
157 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
158 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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| D | HexagonISelDAGToDAG.cpp | 414 } else if (LoadedVT == MVT::v32i32 || LoadedVT == MVT::v16i64 || in SelectIndexedLoad()
531 else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 || in SelectIndexedStore()
572 else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 || in SelectIndexedStore()
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| D | HexagonInstrInfoV60.td | 783 defm : STrivv_pats <v16i64, v32i64>;
817 defm : vS32b_ai_pats <v8i64, v16i64>;
842 defm : LDrivv_pats <v16i64, v32i64>;
870 defm : vL32b_ai_pats <v8i64, v16i64>;
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| D | HexagonInstrInfoVector.td | 82 defm : bitconvert_dblvec<v16i64, v128i8>;
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| D | HexagonInstrInfo.cpp | 2291 if (VT == MVT::v32i32 || VT == MVT::v16i64 || in isValidAutoIncImm()
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| /external/llvm/test/CodeGen/X86/ |
| D | masked_memop.ll | 384 call void @llvm.masked.store.v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32 4, <16 x i1> %mask)
387 declare void @llvm.masked.store.v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32, <16 x i1> %mask)
410 …%res = call <16 x i64> @llvm.masked.load.v16i64(<16 x i64>* %ptrs, i32 4, <16 x i1> %mask, <16 x i…
413 declare <16 x i64> @llvm.masked.load.v16i64(<16 x i64>* %ptrs, i32, <16 x i1> %mask, <16 x i64> %sr…
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| D | masked_gather_scatter.ll | 1539 …%res = call <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32 4, <16 x i1> %mask, <16 x…
1542 declare <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32, <16 x i1> %mask, <16 x i64> %…
1717 call void @llvm.masked.scatter.v16i64(<16 x i64> %src0, <16 x i64*> %ptrs, i32 4, <16 x i1> %mask)
1720 declare void @llvm.masked.scatter.v16i64(<16 x i64> %src0, <16 x i64*> %ptrs, i32, <16 x i1> %mask)
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ctpop64.ll | 8 declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 109 case MVT::v16i64: return "MVT::v16i64"; in getEnumName()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 396 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 279 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } in getCmpSelInstrCost()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 198 def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64
|