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Searched refs:v1i16 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h78 v1i16 = 30, // 1 x i16 enumerator
221 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
327 case v1i16: in getVectorElementType()
413 case v1i16: in getVectorNumElements()
451 case v1i16: return 16; in getSizeInBits()
607 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
DValueTypes.td55 def v1i16 : ValueType<16 , 30>; // 1 x i16 vector value
/external/clang/test/CodeGen/
Dsystemz-abi-vector.c13 typedef __attribute__((vector_size(2))) short v1i16; typedef
66 v1i16 pass_v1i16(v1i16 arg) { return arg; } in pass_v1i16()
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
Darm64-neon-copy.ll857 define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
858 ; CHECK-LABEL: testDUP.v1i16:
/external/llvm/lib/IR/
DValueTypes.cpp157 case MVT::v1i16: return "v1i16"; in getEVTString()
235 case MVT::v1i16: return VectorType::get(Type::getInt16Ty(Context), 1); in getTypeForEVT()
/external/llvm/test/CodeGen/ARM/
Dcttz_vector.ll11 declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
82 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
266 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td341 // D form - v1i8, v1i16, v1i32, v1i64
368 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
404 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
494 // D form - v1i8, v1i16, v1i32, v1i64
DAArch64InstrFormats.td5691 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5704 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5712 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5932 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
5944 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
5959 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5974 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
DAArch64ISelLowering.cpp9887 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp90 case MVT::v1i16: return "MVT::v1i16"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td177 def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16