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Searched refs:v32i64 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h100 v32i64 = 50, // 32 x i64 enumerator
273 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
347 case v32i64: return i64; in getVectorElementType()
381 case v32i64: return 32; in getVectorNumElements()
504 case v32i64: return 2048; in getSizeInBits()
631 if (NumElements == 32) return MVT::v32i64; in getVectorVT()
DValueTypes.td77 def v32i64 : ValueType<2048,50>; // 32 x i64 vector value
/external/llvm/lib/IR/
DValueTypes.cpp177 case MVT::v32i64: return "v32i64"; in getEVTString()
255 case MVT::v32i64: return VectorType::get(Type::getInt64Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
422 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { in RetCC_Hexagon()
548 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1104 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1583 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
1820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom); in HexagonTargetLowering()
2696 case MVT::v32i64: in getRegForInlineAsmConstraint()
2845 case MVT::v32i64: in findRepresentativeClass()
DHexagonInstrInfoVector.td88 defm : bitconvert_dblvec128B<v32i64, v128i16>;
91 defm : bitconvert_dblvec128B<v32i64, v256i8>;
DHexagonRegisterInfo.td229 [v256i8,v128i16,v64i32,v32i64], 2048,
DHexagonInstrInfoV60.td783 defm : STrivv_pats <v16i64, v32i64>;
842 defm : LDrivv_pats <v16i64, v32i64>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp110 case MVT::v32i64: return "MVT::v32i64"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td199 def llvm_v32i64_ty : LLVMType<v32i64>; // 32 x i64