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Searched refs:v4i64 (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
159 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
200 { ISD::SHL, MVT::v4i64, 2 }, in getArithmeticInstrCost()
201 { ISD::SRL, MVT::v4i64, 4 }, in getArithmeticInstrCost()
202 { ISD::SRA, MVT::v4i64, 4 }, in getArithmeticInstrCost()
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
227 { ISD::SDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
231 { ISD::UDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
253 { ISD::SHL, MVT::v4i64, 2 }, // psllq. in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
306 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
328 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
369 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
411 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
486 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
502 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
521 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
[all …]
DX86InstrFragmentsSIMD.td622 // NOTE: all 256-bit integer vector loads are promoted to v4i64
625 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
702 // NOTE: all 256-bit integer vector loads are promoted to v4i64
708 (v4i64 (alignedload256 node:$ptr))>;
785 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
786 Mgt->getBasePtr().getValueType() == MVT::v4i64);
823 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
824 Sc->getBasePtr().getValueType() == MVT::v4i64);
863 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
DX86ISelLowering.cpp1061 setOperationAction(ISD::ROTL, MVT::v4i64, Custom); in X86TargetLowering()
1069 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); in X86TargetLowering()
1074 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); in X86TargetLowering()
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); in X86TargetLowering()
1133 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); in X86TargetLowering()
1136 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1139 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1142 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1152 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom); in X86TargetLowering()
1157 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom); in X86TargetLowering()
[all …]
DX86InstrAVX512.td75 !if (!eq (Size, 256), "v4i64",
81 !if (!eq (Size, 256), "v4i64",
443 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
447 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
451 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
453 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
[all …]
DX86RegisterInfo.td451 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
476 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h97 v4i64 = 47, // 4 x i64 enumerator
252 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
344 case v4i64: in getVectorElementType()
400 case v4i64: in getVectorNumElements()
486 case v4i64: in getSizeInBits()
628 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
DValueTypes.td74 def v4i64 : ValueType<256, 47>; // 4 x i64 vector value
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
394 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll11 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
39 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Dfold-vector-sext-crash.ll6 ; due to an illegal build_vector of type MVT::v4i64.
Davx-cmp.ll61 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
105 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Dvector-popcnt-256.ll42 %out = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %in)
185 %out = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> <i64 256, i64 -1, i64 0, i64 255>)
216 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>)
Dbswap-vector.ll116 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
247 %r = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
348 %bs1 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
349 %bs2 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %bs1)
456 %r = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> <i64 255, i64 -1, i64 65535, i64 16776960>)
Davx2-arith.ll106 ; CHECK: mul-v4i64
116 define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Dvector-tzcnt-256.ll54 %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %in, i1 0)
107 %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %in, i1 -1)
460 %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> <i64 256, i64 -1, i64 0, i64 255>, i1 0)
469 %out = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> <i64 256, i64 -1, i64 0, i64 255>, i1 -1)
527 declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)
/external/llvm/test/CodeGen/AMDGPU/
Dctpop64.ll6 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
75 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
107 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
Dbswap.ll10 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
112 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
Dbitreverse.ll12 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp83 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
87 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
88 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
277 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
DARMRegisterInfo.td375 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
389 def DQuad : RegisterClass<"ARM", [v4i64], 256,
430 def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp88 DstVT = MVT::v4i64; in getZeroExtensionTypes()
113 DstVT = MVT::v4i64; in getZeroExtensionTypes()
126 DstVT = MVT::v4i64; in getZeroExtensionTypes()
633 DecodeVPERM2X128Mask(MVT::v4i64, in EmitAnyX86InstComments()
/external/llvm/lib/IR/
DValueTypes.cpp174 case MVT::v4i64: return "v4i64"; in getEVTString()
252 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp107 case MVT::v4i64: return "MVT::v4i64"; in getEnumName()

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