Searched refs:v64i32 (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 93 v64i32 = 44, // 64 x i32 enumerator
273 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
341 case v64i32: return i32; in getVectorElementType()
376 case v64i32: return 64; in getVectorNumElements()
503 case v64i32: in getSizeInBits()
623 if (NumElements == 64) return MVT::v64i32; in getVectorVT()
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| D | ValueTypes.td | 70 def v64i32 : ValueType<2048,44>; // 32 x i32 vector value
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 171 case MVT::v64i32: return "v64i32"; in getEVTString()
249 case MVT::v64i32: return VectorType::get(Type::getInt32Ty(Context), 64); in getTypeForEVT()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
422 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { in RetCC_Hexagon()
423 LocVT = MVT::v64i32; in RetCC_Hexagon()
424 ValVT = MVT::v64i32; in RetCC_Hexagon()
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
495 } else if (LocVT == MVT::v64i32) { in RetCC_HexagonVector()
548 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1104 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1582 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
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| D | HexagonIntrinsicsV60.td | 71 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
72 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
76 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
77 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
830 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
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| D | HexagonInstrInfoVector.td | 86 defm : bitconvert_dblvec128B<v64i32, v128i16>;
90 defm : bitconvert_dblvec128B<v64i32, v256i8>;
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| D | HexagonRegisterInfo.td | 229 [v256i8,v128i16,v64i32,v32i64], 2048,
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| D | HexagonInstrInfoV60.td | 782 defm : STrivv_pats <v32i32, v64i32>;
841 defm : LDrivv_pats <v32i32, v64i32>;
1547 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 104 case MVT::v64i32: return "MVT::v64i32"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 192 def llvm_v64i32_ty : LLVMType<v64i32>; // 64 x i32
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