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Searched refs:v8i32 (Results 1 – 25 of 37) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
154 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
197 { ISD::SHL, MVT::v8i32, 2 }, in getArithmeticInstrCost()
198 { ISD::SRL, MVT::v8i32, 4 }, in getArithmeticInstrCost()
199 { ISD::SRA, MVT::v8i32, 4 }, in getArithmeticInstrCost()
226 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
230 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
[all …]
DX86InstrSSE.td340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
306 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
328 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
369 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
411 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
486 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
502 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
521 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86ISelLowering.cpp1060 setOperationAction(ISD::ROTL, MVT::v8i32, Custom); in X86TargetLowering()
1067 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); in X86TargetLowering()
1106 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in X86TargetLowering()
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); in X86TargetLowering()
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); in X86TargetLowering()
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in X86TargetLowering()
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in X86TargetLowering()
1143 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); in X86TargetLowering()
1151 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom); in X86TargetLowering()
1156 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom); in X86TargetLowering()
[all …]
DX86InstrAVX512.td44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
442 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
446 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
463 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
464 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
465 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
[all …]
DX86InstrFragmentsSIMD.td770 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
771 Mgt->getBasePtr().getValueType() == MVT::v8i32);
831 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
832 Sc->getBasePtr().getValueType() == MVT::v8i32);
862 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.gather4.ll86 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> unde…
153 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> unde…
179 …%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
205 …%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
218 …%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> un…
272 …%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> unde…
298 …%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
324 …%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
337 …%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> un…
378 …%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
[all …]
Dbswap.ll7 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone
91 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
Dctpop.ll8 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone
128 %ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %val) nounwind readnone
Dsi-sgpr-spill.ll274 …%244 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %243, <32 x i8> %62, <16 x i8> %64, i32 2)
319 …%278 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %277, <32 x i8> %66, <16 x i8> %68, i32 2)
339 …%298 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %297, <32 x i8> %82, <16 x i8> %84, i32 2)
357 …%316 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %315, <32 x i8> %78, <16 x i8> %80, i32 2)
387 …%346 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %345, <32 x i8> %62, <16 x i8> %64, i32 2)
417 …%376 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %375, <32 x i8> %70, <16 x i8> %72, i32 2)
471 …%430 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %429, <32 x i8> %86, <16 x i8> %88, i32 2)
613 …%572 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %571, <32 x i8> %74, <16 x i8> %76, i32 2)
637 …%592 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %591, <32 x i8> %62, <16 x i8> %64, i32 2)
676 declare <4 x float> @llvm.SI.sampled.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32) #1
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h90 v8i32 = 41, // 8 x i32 enumerator
252 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
338 case v8i32: in getVectorElementType()
391 case v8i32: in getVectorNumElements()
485 case v8i32: in getSizeInBits()
620 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
DValueTypes.td67 def v8i32 : ValueType<256, 41>; // 8 x i32 vector value
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
392 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp89 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
90 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
100 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
121 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td2117 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
2222 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2233 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2239 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2308 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2314 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2316 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2318 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2319 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2324 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
[all …]
DSIRegisterInfo.td211 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add SGPR_256)> {
239 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add VGPR_256)> {
DSIISelLowering.cpp61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); in SITargetLowering()
69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom); in SITargetLowering()
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom); in SITargetLowering()
167 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand); in SITargetLowering()
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) { in SITargetLowering()
/external/llvm/test/CodeGen/ARM/
Disel-v8i32-crash.ll9 ; when we have a vector length of 8, due to use of v8i32 types.
/external/llvm/test/CodeGen/X86/
Dvector-popcnt-256.ll95 %out = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %in)
194 …%out = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i3…
217 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>)
Dbswap-vector.ll115 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
200 %r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v)
338 %bs1 = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v)
339 %bs2 = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %bs1)
440 …%r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> <i32 0, i32 1, i32 -1, i32 2, i32 -3, i32 4, i32 -…
Dmasked_memop.ll165 …%res = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %addr, i32 4, <8 x i1>%mask, <8 x i32>%ds…
187 …%res = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %addr, i32 4, <8 x i1> %mask, <8 x i32> z…
198 call void @llvm.masked.store.v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask)
332 declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
340 declare <8 x i32> @llvm.masked.load.v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)
Dvector-tzcnt-256.ll172 %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %in, i1 0)
237 %out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %in, i1 -1)
478 …%out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i32…
487 …%out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i32…
528 declare <8 x i32> @llvm.cttz.v8i32(<8 x i32>, i1)
Dmasked_gather_scatter.ll55 declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> , i32, <8 x i1> , <8 x i32> )
230 declare void @llvm.masked.scatter.v8i32(<8 x i32> , <8 x i32*> , i32 , <8 x i1> )
272 …%a = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, …
274 …call void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 …
319 …%gt1 = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.random, i32 4, <8 x i1> %imask, <8…
320 …%gt2 = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.random, i32 4, <8 x i1> %imask, <8…
450 …%res = call <8 x i32 > @llvm.masked.gather.v8i32(<8 x i32*>%arrayidx, i32 4, <8 x i1> <i1 true, i…
512 …%res = call <8 x i32 > @llvm.masked.gather.v8i32(<8 x i32*>%arrayidx, i32 4, <8 x i1> <i1 true, i…
/external/llvm/lib/IR/
DValueTypes.cpp168 case MVT::v8i32: return "v8i32"; in getEVTString()
246 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8); in getTypeForEVT()
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll73 declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)

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