/external/valgrind/VEX/priv/ |
D | host_generic_reg_alloc2.c | 119 HReg vreg; member 181 if (HRegUsage__contains(®_usages_in[m], state[k].vreg)) in findMostDistantlyMentionedVReg() 195 static void sanity_check_spill_offset ( VRegLR* vreg ) in sanity_check_spill_offset() argument 197 switch (vreg->reg_class) { in sanity_check_spill_offset() 199 vassert(0 == ((UShort)vreg->spill_offset % 16)); break; in sanity_check_spill_offset() 201 vassert(0 == ((UShort)vreg->spill_offset % 8)); break; in sanity_check_spill_offset() 483 (*ppReg)(rreg_state[z].vreg); \ in doRegisterAllocation() 523 rreg_state[j].vreg = INVALID_HREG; in doRegisterAllocation() 604 HReg vreg = reg_usage_arr[ii].vRegs[j]; in doRegisterAllocation() local 605 vassert(hregIsVirtual(vreg)); in doRegisterAllocation() [all …]
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/external/v8/test/unittests/compiler/ |
D | instruction-sequence-unittest.h | 51 TestOperand(TestOperandType type, VReg vreg, int value = kNoValue) 52 : type_(type), vreg_(vreg), value_(value) {} in type_() 66 static TestOperand Reg(VReg vreg, int index = kNoValue) { 69 return TestOperand(type, vreg, index); 74 static TestOperand Slot(VReg vreg, int index = kNoValue) { 77 return TestOperand(type, vreg, index); 87 static TestOperand Use(VReg vreg) { return TestOperand(kNone, vreg); } in Use() argument 91 static TestOperand Unique(VReg vreg) { return TestOperand(kUnique, vreg); } in Unique() argument 93 static TestOperand UniqueReg(VReg vreg) { in UniqueReg() argument 94 return TestOperand(kUniqueRegister, vreg); in UniqueReg() [all …]
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D | instruction-sequence-unittest.cc | 148 VReg vreg = NewReg(); in Define() local 149 InstructionOperand outputs[1]{ConvertOutputOp(vreg, output_op)}; in Define() 151 return vreg; in Define() 192 VReg vreg) { in SetInput() argument 193 CHECK(vreg.value_ != kNoValue); in SetInput() 194 phi->SetInput(input, vreg.value_); in SetInput() 200 VReg vreg = NewReg(); in DefineConstant() local 201 sequence()->AddConstant(vreg.value_, Constant(imm)); in DefineConstant() 202 InstructionOperand outputs[1]{ConstantOperand(vreg.value_)}; in DefineConstant() 204 return vreg; in DefineConstant() [all …]
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D | live-range-unittest.cc | 435 TopLevelLiveRange* vreg = TestRangeBuilder(zone()).Id(2).Build(0, 100); in TEST_F() local 436 EXPECT_EQ(2, vreg->vreg()); in TEST_F() 437 EXPECT_EQ(0, vreg->relative_id()); in TEST_F() 441 vreg->SetSplinter(splinter); in TEST_F() 442 vreg->Splinter(LifetimePosition::FromInt(4), LifetimePosition::FromInt(12), in TEST_F() 445 EXPECT_EQ(101, splinter->vreg()); in TEST_F() 448 LiveRange* child = vreg->SplitAt(LifetimePosition::FromInt(50), zone()); in TEST_F() 458 vreg->Merge(splinter, zone()); in TEST_F()
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D | coalesced-live-ranges-unittest.cc | 61 int id = c->TopLevel()->vreg(); in RemoveConflicts() 63 seen.insert(c->TopLevel()->vreg()); in RemoveConflicts() 80 found_ids.insert(conflict->TopLevel()->vreg()); in IsRangeConflictingWith()
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/external/v8/src/compiler/ |
D | live-range-separator.cc | 50 DCHECK_NULL(data->live_ranges()[splinter->vreg()]); in CreateSplinter() 51 data->live_ranges()[splinter->vreg()] = splinter; in CreateSplinter() 55 TRACE("creating splinter for range %d between %d and %d\n", range->vreg(), in CreateSplinter() 108 for (size_t vreg = 0; vreg < virt_reg_count; ++vreg) { in Splinter() local 109 TopLevelLiveRange *range = data()->live_ranges()[vreg]; in Splinter() 150 int to_remove = range->vreg(); in Merge()
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D | register-allocator.cc | 707 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument 709 vreg_(vreg), in TopLevelLiveRange() 725 return IsSplinter() ? splintered_from()->vreg() : vreg(); in debug_virt_reg() 742 TRACE("Live Range %d will be spilled only in deferred blocks.\n", vreg()); in TryCommitSpillInDeferredBlock() 999 TRACE("Shorten live range %d to [%d\n", vreg(), start.value()); in ShortenTo() 1009 TRACE("Ensure live range %d in interval [%d %d[\n", vreg(), start.value(), in EnsureInterval() 1030 TRACE("Add to live range %d interval [%d %d[\n", vreg(), start.value(), in AddUseInterval() 1057 TRACE("Add to live range %d use position %d\n", vreg(), pos.value()); in AddUsePosition() 1103 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() in operator <<() 1236 os << range->vreg() << " "; in Print() [all …]
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D | greedy-allocator.cc | 65 TRACE("Scheduling live range %d:%d.\n", range->TopLevel()->vreg(), in Schedule() 86 range->TopLevel()->vreg(), range->relative_id()); in AssignRangeToRegister() 93 range->TopLevel()->vreg(), range->relative_id()); in AssignRangeToRegister() 148 if (j == range->vreg()) continue; in GroupLiveRanges() 275 TRACE("Attempting to allocate live range %d:%d.\n", range->TopLevel()->vreg(), in TryAllocateLiveRange() 325 RegisterName(free_reg), range->TopLevel()->vreg(), in TryAllocateLiveRange() 335 RegisterName(free_reg), range->TopLevel()->vreg(), in TryAllocateLiveRange() 358 TRACE("Evicted range %d%d.\n", conflict->TopLevel()->vreg(), in EvictAndRescheduleConflicts()
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D | graph-visualizer.cc | 234 void PrintLiveRange(LiveRange* range, const char* type, int vreg); 525 int vreg = range->vreg(); in PrintLiveRangeChain() local 527 PrintLiveRange(child, type, vreg); in PrintLiveRangeChain() 533 int vreg) { in PrintLiveRange() argument 536 os_ << vreg << ":" << range->relative_id() << " " << type; in PrintLiveRange() 566 os_ << " " << vreg; in PrintLiveRange()
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D | register-allocator-verifier.cc | 159 int vreg = unallocated->virtual_register(); in BuildConstraint() local 160 constraint->virtual_register_ = vreg; in BuildConstraint() 162 constraint->type_ = sequence()->IsFloat(vreg) ? kDoubleSlot : kSlot; in BuildConstraint() 168 if (sequence()->IsFloat(vreg)) { in BuildConstraint() 188 if (sequence()->IsFloat(vreg)) { in BuildConstraint() 195 constraint->type_ = sequence()->IsFloat(vreg) ? kDoubleSlot : kSlot; in BuildConstraint()
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/external/vixl/src/vixl/a64/ |
D | simulator-a64.cc | 652 (lane_size_in_bytes == kSRegSizeInBytes) ? vreg(code).Get<float>(lane) in PrintVRegisterFPHelper() 653 : vreg(code).Get<double>(lane); in PrintVRegisterFPHelper() 1996 LogicVRegister(vreg(dst)).SetUint(kFormatD, 1, xreg(src)); in VisitFPIntegerConvert() 1999 set_xreg(dst, LogicVRegister(vreg(src)).Uint(kFormatD, 1)); in VisitFPIntegerConvert() 2164 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing1Source() 2165 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing1Source() 2174 case FABS_s: fabs_(kFormatS, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source() 2175 case FABS_d: fabs_(kFormatD, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source() 2176 case FNEG_s: fneg(kFormatS, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source() 2177 case FNEG_d: fneg(kFormatD, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source() [all …]
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/external/v8/test/cctest/compiler/ |
D | test-instruction.cc | 84 UnallocatedOperand Unallocated(int vreg) { in Unallocated() argument 85 return UnallocatedOperand(UnallocatedOperand::ANY, vreg); in Unallocated() 280 int vreg = 15; in TEST() local 282 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST() 283 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST() 284 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST() 285 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg)}; in TEST() 288 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST() 289 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST() 290 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST() [all …]
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_wm_debug.c | 45 else if( value - c->vreg >= 0 && in brw_wm_print_value() 46 value - c->vreg < BRW_WM_MAX_VREG) in brw_wm_print_value() 47 printf("r%ld", (long) (value - c->vreg)); in brw_wm_print_value()
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D | brw_wm.c | 285 void *vreg = c->vreg; in do_wm_prog() local 290 c->vreg = vreg; in do_wm_prog() 311 c->vreg = rzalloc_array(c, struct brw_wm_value, BRW_WM_MAX_VREG); in do_wm_prog()
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D | brw_wm_pass0.c | 52 memset(&c->vreg[c->nr_vreg], 0, sizeof(*c->vreg)); in get_value() 53 return &c->vreg[c->nr_vreg++]; in get_value()
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/external/v8/src/x64/ |
D | assembler-x64-inl.h | 223 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument 229 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix() 232 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix() 237 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument 241 XMMRegister ivreg = {vreg.code()}; in emit_vex_prefix() 247 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument 253 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix() 256 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix() 261 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, in emit_vex_prefix() argument 265 XMMRegister ivreg = {vreg.code()}; in emit_vex_prefix()
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D | assembler-x64.cc | 3786 void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) { in bmi1q() argument 3789 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); in bmi1q() 3795 void Assembler::bmi1q(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1q() argument 3798 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); in bmi1q() 3804 void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) { in bmi1l() argument 3807 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); in bmi1l() 3813 void Assembler::bmi1l(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1l() argument 3816 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); in bmi1l() 3954 void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2q() argument 3958 emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1); in bmi2q() [all …]
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/external/llvm/test/CodeGen/PowerPC/ |
D | quadint-return.ll | 17 ; CHECK: %X3<def> = COPY %vreg 18 ; CHECK-NEXT: %X4<def> = COPY %vreg
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/external/llvm/test/CodeGen/AArch64/ |
D | tailcall_misched_graph.ll | 29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1> 30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2> 31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4>
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D | arm64-fast-isel-rem.ll | 7 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr 9 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
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/external/llvm/test/CodeGen/ARM/ |
D | misched-copy-arm.ll | 36 ; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1> 37 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]] 38 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
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D | fast-isel-shift-materialize.ll | 6 ; When materializing the '2' for the shifts below, the second shift kills the vreg 7 ; we materialize in to. However, the first shift was also killing that vreg.
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D | fast-isel-remat-same-constant.ll | 7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou… 9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
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D | fast-isel-update-valuemap-for-extract.ll | 6 ; This test ensures that when fast-isel rewrites uses of the vreg for %tmp29, it also
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/external/vixl/test/ |
D | test-utils-a64.cc | 145 const VRegister& vreg) { in Equal128() argument 146 VIXL_ASSERT(vreg.Is128Bits()); in Equal128() 148 vec128_t result = core->qreg(vreg.code()); in Equal128()
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