/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_wm_pass1.c | 42 if (inst->writemask & (1<<i)) { in get_tracked_mask() 44 inst->writemask &= ~(1<<i); in get_tracked_mask() 50 return inst->writemask; in get_tracked_mask() 123 GLuint writemask; in brw_wm_pass1() local 144 writemask = get_tracked_mask(c, inst); in brw_wm_pass1() 145 if (!writemask) { in brw_wm_pass1() 166 read0 = writemask; in brw_wm_pass1() 180 read0 = writemask; in brw_wm_pass1() 181 read1 = writemask; in brw_wm_pass1() 186 read0 = writemask; in brw_wm_pass1() [all …]
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D | brw_wm_debug.c | 101 if (inst->writemask != WRITEMASK_XYZW) in brw_wm_print_insn() 103 GET_BIT(inst->writemask, 0) ? "x" : "", in brw_wm_print_insn() 104 GET_BIT(inst->writemask, 1) ? "y" : "", in brw_wm_print_insn() 105 GET_BIT(inst->writemask, 2) ? "z" : "", in brw_wm_print_insn() 106 GET_BIT(inst->writemask, 3) ? "w" : ""); in brw_wm_print_insn()
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D | brw_wm_pass0.c | 247 GLuint writemask ) in pass0_set_dst() argument 253 if (writemask & (1<<i)) { in pass0_set_dst() 259 out->writemask = writemask; in pass0_set_dst() 317 GLuint writemask = inst->DstReg.WriteMask; in translate_insn() local 341 pass0_set_dst(c, out, inst, writemask); in translate_insn() 353 GLuint writemask = inst->DstReg.WriteMask; in pass0_precalc_mov() local 368 if (writemask & (1 << i)) { in pass0_precalc_mov()
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D | brw_vec4_visitor.cpp | 234 if (dst.writemask != WRITEMASK_XYZW) { in emit_math1_gen6() 304 if (dst.writemask != WRITEMASK_XYZW) { in emit_math2_gen6() 447 this->writemask = WRITEMASK_XYZW; in dst_reg() 449 this->writemask = (1 << type->vector_elements) - 1; in dst_reg() 808 dst.writemask = (1 << c->key.gl_fixed_input_size[i]) - 1; in visit() 862 reg->writemask = WRITEMASK_X; in visit() 865 reg->writemask = WRITEMASK_Y; in visit() 1048 result_dst.writemask = (1 << ir->type->vector_elements) - 1; in visit() 1578 dst->writemask = (1 << type->vector_elements) - 1; in emit_block_move() 1628 if (dst.writemask & (1 << i)) { in try_rewrite_rhs_to_dst() [all …]
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D | brw_vec4.cpp | 123 if (!(reg.writemask & (1 << i))) in src_reg() 152 this->writemask = WRITEMASK_XYZW; in init() 169 int writemask) in dst_reg() argument 176 this->writemask = writemask; in dst_reg() 195 this->writemask = WRITEMASK_XYZW; in dst_reg() 735 if (!(inst->dst.writemask & (1 << i))) in opt_compute_to_mrf() 783 if (scan_inst->dst.writemask & (1 << i) && in opt_compute_to_mrf() 853 scan_inst->dst.writemask &= inst->dst.writemask; in opt_compute_to_mrf()
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D | brw_fs_vector_splitting.cpp | 273 unsigned int writemask; in visit_leave() local 280 writemask = 1; in visit_leave() 283 writemask = 1 << i; in visit_leave() 296 NULL, writemask)); in visit_leave()
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D | brw_vs_emit.c | 438 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); in unalias1() 464 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); in unalias2() 493 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); in unalias3() 664 dst.dw1.bits.writemask != 0xf) in emit_math1_gen4() 747 dst.dw1.bits.writemask != 0xf) in emit_math2_gen4() 824 if (dst.dw1.bits.writemask & WRITEMASK_X) { in emit_exp_noalias() 847 if (dst.dw1.bits.writemask & WRITEMASK_Y) { in emit_exp_noalias() 852 if (dst.dw1.bits.writemask & WRITEMASK_Z) { in emit_exp_noalias() 867 if (dst.dw1.bits.writemask & WRITEMASK_W) { in emit_exp_noalias() 882 bool need_tmp = (dst.dw1.bits.writemask != 0xf || in emit_log_noalias() [all …]
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D | brw_vec4_emit.cpp | 66 reg.dw1.bits.writemask = inst->dst.writemask; in setup_attributes() 165 brw_reg.dw1.bits.writemask = dst.writemask; in get_dst() 171 brw_reg.dw1.bits.writemask = dst.writemask; in get_dst() 286 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); in generate_math1_gen6() 319 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); in generate_math2_gen6()
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D | brw_vec4_reg_allocate.cpp | 339 temp.writemask = 0; in spill_reg() 341 temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c)); in spill_reg() 342 assert(temp.writemask != 0); in spill_reg()
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
D | radeon_pair_regalloc.c | 238 unsigned int writemask, in find_class() argument 248 if (classes[i].Writemasks[j] == writemask) { in find_class() 281 unsigned int writemask = rc_variable_writemask_sum(variable); in variable_get_class() local 293 writemask = RC_MASK_XYZW; in variable_get_class() 299 class_index = find_class(classes, writemask, 3); in variable_get_class() 314 writemask, c.Writemasks[i]); in variable_get_class() 379 class_index = find_class(classes, writemask, in variable_get_class() 388 variable->Dst.Index, writemask); in variable_get_class() 418 static int get_reg_id(unsigned int index, unsigned int writemask) in get_reg_id() argument 420 assert(writemask); in get_reg_id() [all …]
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D | radeon_rename_regs.c | 72 unsigned writemask; in rc_rename_regs() local 86 writemask = rc_variable_writemask_sum(var); in rc_rename_regs() 87 rc_variable_change_dst(var, new_index, writemask); in rc_rename_regs()
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D | radeon_variable.c | 320 unsigned int writemask; in get_variable_pair_helper() local 334 writemask = sub_inst->WriteMask; in get_variable_pair_helper() 337 writemask = sub_inst->OutputWriteMask; in get_variable_pair_helper() 339 writemask = 0; in get_variable_pair_helper() 342 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask, in get_variable_pair_helper() 392 unsigned int writemask = 0; in rc_variable_writemask_sum() local 394 writemask |= var->Dst.WriteMask; in rc_variable_writemask_sum() 397 return writemask; in rc_variable_writemask_sum()
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D | radeon_opcodes.c | 524 unsigned int writemask, in rc_compute_sources_for_writemask() argument 537 if (!writemask) in rc_compute_sources_for_writemask() 542 srcmasks[src] |= writemask; in rc_compute_sources_for_writemask() 545 srcmasks[src] |= writemask; in rc_compute_sources_for_writemask()
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/external/mesa3d/src/gallium/drivers/llvmpipe/ |
D | lp_bld_depth.c | 276 if (stencil[0].writemask != 0xff || in lp_build_stencil_op() 277 (stencil[1].enabled && front_facing != NULL && stencil[1].writemask != 0xff)) { in lp_build_stencil_op() 279 LLVMValueRef writemask = lp_build_const_int_vec(bld->gallivm, bld->type, in lp_build_stencil_op() local 280 stencil[0].writemask); in lp_build_stencil_op() 281 … if (stencil[1].enabled && stencil[1].writemask != stencil[0].writemask && front_facing != NULL) { in lp_build_stencil_op() 283 stencil[1].writemask); in lp_build_stencil_op() 284 writemask = lp_build_select(bld, front_facing, writemask, back_writemask); in lp_build_stencil_op() 287 mask = LLVMBuildAnd(builder, mask, writemask, ""); in lp_build_stencil_op() 773 if (depth->writemask) { in lp_build_depth_stencil_test() 827 if ((depth->enabled && depth->writemask) || in lp_build_depth_stencil_test() [all …]
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/external/mesa3d/src/gallium/drivers/svga/ |
D | svga_tgsi_insn.c | 924 writemask(temp, channel), in emit_div() 1052 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 )) in emit_sincos() 1075 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0)) in emit_sin() 1100 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 )) in emit_cos() 1134 writemask( temp0, dst.mask ), src0, one, zero )) in emit_ssg() 1139 writemask( temp1, dst.mask ), negate( src0 ), negate( one ), in emit_ssg() 1198 writemask( temp, TGSI_WRITEMASK_XYZ ), in emit_kil() 1213 writemask( temp, TGSI_WRITEMASK_XYZ ), in emit_kil() 1502 writemask( tmp, TGSI_WRITEMASK_W ), in emit_tex2() 1597 writemask(dst, srcWritemask), in emit_tex_swizzle() [all …]
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D | svga_pipe_depthstencil.c | 93 ds->stencil_writemask = templ->stencil[0].writemask & 0xff; in svga_create_depth_stencil_state() 105 ds->stencil_writemask = templ->stencil[1].writemask & 0xff; in svga_create_depth_stencil_state() 112 ds->zwriteenable = templ->depth.writemask; in svga_create_depth_stencil_state()
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/external/mesa3d/src/mesa/program/ |
D | ir_to_mesa.cpp | 105 dst_reg(gl_register_file file, int writemask) in dst_reg() argument 109 this->writemask = writemask; in dst_reg() 118 this->writemask = 0; in dst_reg() 127 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in dst_reg 146 this->writemask = WRITEMASK_XYZW; in dst_reg() 399 assert(dst.writemask != 0); in emit() 435 int done_mask = ~dst.writemask; in emit_scalar() 469 inst->dst.writemask = this_mask; in emit_scalar() 513 int done_mask = ~dst.writemask; in emit_scs() 521 if (scs_mask != unsigned(dst.writemask)) { in emit_scs() [all …]
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/external/mesa3d/src/mesa/state_tracker/ |
D | st_glsl_to_tgsi.cpp | 148 st_dst_reg(gl_register_file file, int writemask, int type) in st_dst_reg() argument 152 this->writemask = writemask; in st_dst_reg() 163 this->writemask = 0; in st_dst_reg() 172 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in st_dst_reg 194 this->writemask = WRITEMASK_XYZW; in st_dst_reg() 596 assert(dst.writemask != 0); in emit() 708 int done_mask = ~dst.writemask; in emit_scalar() 742 inst->dst.writemask = this_mask; in emit_scalar() 798 int done_mask = ~dst.writemask; in emit_scs() 806 if (scs_mask != unsigned(dst.writemask)) { in emit_scs() [all …]
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D | st_atom_depth.c | 107 dsa->depth.writemask = ctx->Depth.Mask; in update_depth_stencil_alpha() 118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff; in update_depth_stencil_alpha() 129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff; in update_depth_stencil_alpha()
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/external/mesa3d/src/gallium/drivers/r300/ |
D | r300_hyperz.c | 176 assert(!dsa->dsa.depth.writemask); in r300_update_hyperz() 193 if (dsa->dsa.depth.writemask) { in r300_update_hyperz() 225 return s->enabled && s->writemask && in r300_dsa_writes_stencil() 237 if (dsa->depth.enabled && dsa->depth.writemask && in r300_dsa_writes_depth_stencil()
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/external/mesa3d/src/gallium/docs/source/cso/ |
D | dsa.rst | 23 writemask 40 writemask 41 Stencil test writemask; this controls which bits of the stencil buffer
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/external/mesa3d/src/gallium/auxiliary/util/ |
D | u_blit.c | 107 ctx->dsa_write_depth.depth.writemask = 1; in util_create_blit() 115 ctx->dsa_write_stencil.stencil[0].writemask = 0xff; in util_create_blit() 202 set_fragment_shader(struct blit_state *ctx, uint writemask, in set_fragment_shader() argument 205 if (!ctx->fs[pipe_tex][writemask]) { in set_fragment_shader() 208 ctx->fs[pipe_tex][writemask] = in set_fragment_shader() 211 writemask); in set_fragment_shader() 214 cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][writemask]); in set_fragment_shader() 435 uint writemask, uint zs_writemask) in util_blit_pixels() argument 476 assert((writemask && !zs_writemask && !is_depth && !is_stencil) || in util_blit_pixels() 477 (!writemask && (blit_depth || blit_stencil))); in util_blit_pixels() [all …]
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D | u_simple_shaders.c | 117 unsigned writemask ) in util_make_fragment_tex_shader_writemask() argument 141 if (writemask != TGSI_WRITEMASK_XYZW) { in util_make_fragment_tex_shader_writemask() 148 ureg_writemask(out, writemask), in util_make_fragment_tex_shader_writemask()
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
D | tgsi_text.c | 336 uint *writemask ) in parse_opt_writemask() argument 344 *writemask = TGSI_WRITEMASK_NONE; in parse_opt_writemask() 348 *writemask |= TGSI_WRITEMASK_X; in parse_opt_writemask() 352 *writemask |= TGSI_WRITEMASK_Y; in parse_opt_writemask() 356 *writemask |= TGSI_WRITEMASK_Z; in parse_opt_writemask() 360 *writemask |= TGSI_WRITEMASK_W; in parse_opt_writemask() 363 if (*writemask == TGSI_WRITEMASK_NONE) { in parse_opt_writemask() 371 *writemask = TGSI_WRITEMASK_XYZW; in parse_opt_writemask() 683 uint writemask; in parse_dst_operand() local 696 if (!parse_opt_writemask( ctx, &writemask )) in parse_dst_operand() [all …]
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D | tgsi_dump.c | 191 uint writemask ) in _dump_writemask() argument 193 if (writemask != TGSI_WRITEMASK_XYZW) { in _dump_writemask() 195 if (writemask & TGSI_WRITEMASK_X) in _dump_writemask() 197 if (writemask & TGSI_WRITEMASK_Y) in _dump_writemask() 199 if (writemask & TGSI_WRITEMASK_Z) in _dump_writemask() 201 if (writemask & TGSI_WRITEMASK_W) in _dump_writemask()
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