| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_vec.c | 67 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
165 p->R21.d[1] = (uint32_t)(r1); in CRYPTO_poly1305_init()
166 p->R21.d[3] = (uint32_t)(r1 >> 32); in CRYPTO_poly1305_init()
205 r1 = ((uint64_t)p->R21.d[3] << 32) | (uint64_t)p->R21.d[1]; in poly1305_first_block()
236 p->R21.v = _mm_shuffle_epi32( in poly1305_first_block()
247 p->S21.v = _mm_mul_epu32(p->R21.v, FIVE); in poly1305_first_block()
258 p->R21.d[1] = (uint32_t)(r1); in poly1305_first_block()
259 p->R21.d[3] = (uint32_t)(r1 >> 32); in poly1305_first_block()
302 T1 = _mm_mul_epu32(H0, p->R21.v); in poly1305_blocks()
322 T5 = _mm_mul_epu32(H1, p->R21.v); in poly1305_blocks()
[all …]
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| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 14 branch_points: R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22,
27 # Note that the builders have produced R21 tagged artifacts beginning 2266.0.0
30 # R21 actual branchpoint is 2465.0.0
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 66 def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>;
96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
147 add R23, R22, R21, R20, R19, R18, R17, R16
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| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
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| /external/libgdx/extensions/gdx-bullet/jni/src/bullet/BulletCollision/CollisionDispatch/ |
| D | btBoxBoxDetector.cpp | 271 btScalar A[3],B[3],R11,R12,R13,R21,R22,R23,R31,R32,R33, in dBoxBox2() local
289 R21 = dDOT44(R1+1,R2+0); R22 = dDOT44(R1+1,R2+1); R23 = dDOT44(R1+1,R2+2); in dBoxBox2()
293 Q21 = btFabs(R21); Q22 = btFabs(R22); Q23 = btFabs(R23); in dBoxBox2()
363 TST(pp[2]*R21-pp[1]*R31,(A[1]*Q31+A[2]*Q21+B[1]*Q13+B[2]*Q12),0,-R31,R21,7); in dBoxBox2()
373 TST(pp[1]*R11-pp[0]*R21,(A[0]*Q21+A[1]*Q11+B[1]*Q33+B[2]*Q32),-R21,R11,0,13); in dBoxBox2()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.h | 63 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
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| D | HexagonRegisterInfo.cpp | 82 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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| D | HexagonFrameLowering.cpp | 659 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22, in insertCFIInstructionsAt()
803 case Hexagon::R21: in getSpillFunctionFor()
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| D | HexagonRegisterInfo.td | 107 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 213 R21, R22, R23, R24, R25, R26, R27, R28,
222 R21, R22, R23, R24, R25, R26, R27, R28,
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| D | PPCFrameLowering.cpp | 148 {PPC::R21, -44}, in getCalleeSavedSpillSlots()
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 169 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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| /external/valgrind/VEX/orig_ppc32/ |
| D | return0.orig | 4006 63: GETL R21, t50
4014 69: PUTL t54, R21
4698 6: PUTL t4, R21
6097 6: GETL R21, t4
6318 120: GETL R21, t96
6326 126: PUTL t100, R21
9179 3: PUTL t2, R21
9194 12: GETL R21, t10
9237 1: PUTL t0, R21
10043 3: PUTL t2, R21
[all …]
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| D | date.orig | 4006 63: GETL R21, t50
4014 69: PUTL t54, R21
4698 6: PUTL t4, R21
6097 6: GETL R21, t4
6318 120: GETL R21, t96
6326 126: PUTL t100, R21
9179 3: PUTL t2, R21
9194 12: GETL R21, t10
9237 1: PUTL t0, R21
10206 3: PUTL t2, R21
[all …]
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 533 Register = Hexagon::R21; in compoundRegisterMap()
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| D | HexagonMCDuplexInfo.cpp | 675 case Hexagon::R21: in addOps()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 497 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, in DecodeIntRegsRegisterClass()
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