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Searched refs:SUnit (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DResourcePriorityQueue.h31 struct resource_sort : public std::binary_function<SUnit*, SUnit*, bool> {
35 bool operator()(const SUnit* left, const SUnit* right) const;
40 std::vector<SUnit> *SUnits;
49 std::vector<SUnit*> Queue;
71 std::vector<SUnit*> Packet;
82 void initNodes(std::vector<SUnit> &sunits) override;
84 void addNode(const SUnit *SU) override { in addNode()
88 void updateNode(const SUnit *SU) override {} in updateNode()
106 signed SUSchedulingCost (SUnit *SU);
110 void initNumRegDefsLeft(SUnit *SU);
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DScheduleDAG.h28 class SUnit; variable
76 PointerIntPair<SUnit *, 2, Kind> Dep;
101 SDep(SUnit *S, Kind kind, unsigned Reg) in SDep()
119 SDep(SUnit *S, OrderKind kind) in SDep()
160 SUnit *getSUnit() const { in getSUnit()
165 void setSUnit(SUnit *SU) { in setSUnit()
261 class SUnit {
268 SUnit *OrigNode; // If not this, the node from which
325 SUnit(SDNode *node, unsigned nodenum)
341 SUnit(MachineInstr *instr, unsigned nodenum)
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DLatencyPriorityQueue.h25 struct latency_sort : public std::binary_function<SUnit*, SUnit*, bool> {
29 bool operator()(const SUnit* left, const SUnit* right) const;
34 std::vector<SUnit> *SUnits;
43 std::vector<SUnit*> Queue;
52 void initNodes(std::vector<SUnit> &sunits) override { in initNodes()
57 void addNode(const SUnit *SU) override { in addNode()
61 void updateNode(const SUnit *SU) override { in updateNode()
80 void push(SUnit *U) override;
82 SUnit *pop() override;
84 void remove(SUnit *SU) override;
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DMachineScheduler.h198 virtual SUnit *pickNode(bool &IsTopNode) = 0;
205 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
209 virtual void releaseTopNode(SUnit *SU) = 0;
212 virtual void releaseBottomNode(SUnit *SU) = 0;
248 const SUnit *NextClusterPred;
249 const SUnit *NextClusterSucc;
288 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
295 bool addEdge(SUnit *SuccSU, const SDep &PredDep);
316 const SUnit *getNextClusterPred() const { return NextClusterPred; } in getNextClusterPred()
318 const SUnit *getNextClusterSucc() const { return NextClusterSucc; } in getNextClusterSucc()
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DScheduleDAGInstrs.h36 SUnit *SU;
38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
51 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
58 SUnit *SU;
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} in PhysRegSUOper()
128 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
155 std::vector<SUnit *> PendingLoads;
179 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
192 SUnit *newSUnit(MachineInstr *MI);
195 SUnit *getSUnit(MachineInstr *MI) const;
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DScheduleHazardRecognizer.h20 class SUnit; variable
60 virtual HazardType getHazardType(SUnit *m, int Stalls = 0) {
71 virtual void EmitInstruction(SUnit *) {} in EmitInstruction() argument
78 virtual unsigned PreEmitNoops(SUnit *) { in PreEmitNoops() argument
85 virtual bool ShouldPreferAnother(SUnit *) { in ShouldPreferAnother() argument
DDFAPacketizer.h41 class SUnit; variable
142 std::map<MachineInstr*, SUnit*> MIToSUnit;
201 virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { in isLegalToPacketizeTogether()
207 virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { in isLegalToPruneDependencies()
/external/llvm/lib/CodeGen/
DScheduleDAG.cpp52 EntrySU = SUnit(); in clearDAG()
53 ExitSU = SUnit(); in clearDAG()
65 bool SUnit::addPred(const SDep &D, bool Required) { in addPred()
76 SUnit *PredSU = I->getSUnit(); in addPred()
95 SUnit *N = D.getSUnit(); in addPred()
133 void SUnit::removePred(const SDep &D) { in removePred()
141 SUnit *N = D.getSUnit(); in removePred()
178 void SUnit::setDepthDirty() { in setDepthDirty()
180 SmallVector<SUnit*, 8> WorkList; in setDepthDirty()
183 SUnit *SU = WorkList.pop_back_val(); in setDepthDirty()
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DLatencyPriorityQueue.cpp23 bool latency_sort::operator()(const SUnit *LHS, const SUnit *RHS) const { in operator ()()
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { in getSingleUnscheduledPred()
57 SUnit *OnlyAvailablePred = nullptr; in getSingleUnscheduledPred()
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in getSingleUnscheduledPred()
60 SUnit &Pred = *I->getSUnit(); in getSingleUnscheduledPred()
73 void LatencyPriorityQueue::push(SUnit *SU) { in push()
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in push()
92 void LatencyPriorityQueue::scheduledNode(SUnit *SU) { in scheduledNode()
93 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in scheduledNode()
105 void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) { in AdjustPriorityOfUnscheduledPreds()
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DMachineScheduler.cpp521 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) { in canAddEdge()
525 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) { in addEdge()
542 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc()
543 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
570 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors()
571 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
581 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred()
582 SUnit *PredSU = PredEdge->getSUnit(); in releasePred()
609 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { in releasePredecessors()
610 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in releasePredecessors()
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DScheduleDAGInstrs.cpp247 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps()
259 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
290 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps()
306 SUnit *DefSU = I->SU; in addPhysRegDeps()
385 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { in addVRegDefDeps()
423 SUnit *UseSU = I->SU; in addVRegDefDeps()
460 SUnit *DefSU = V2SU.SU; in addVRegDefDeps()
494 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { in addVRegUseDeps()
640 const DataLayout &DL, SUnit *SUa, SUnit *SUb, in iterateChainSucc()
641 SUnit *ExitSU, unsigned *Depth, in iterateChainSucc()
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DScheduleDAGPrinter.cpp42 static bool isNodeHidden(const SUnit *Node) { in isNodeHidden()
46 static std::string getNodeIdentifierLabel(const SUnit *Node, in getNodeIdentifierLabel()
56 static std::string getEdgeAttributes(const SUnit *Node, in getEdgeAttributes()
67 std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph);
68 static std::string getNodeAttributes(const SUnit *N, in getNodeAttributes()
80 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU, in getNodeLabel()
DPostRASchedulerList.cpp117 std::vector<SUnit*> PendingQueue;
129 std::vector<SUnit*> Sequence;
179 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
180 void ReleaseSuccessors(SUnit *SU);
181 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
245 if (SUnit *SU = Sequence[i]) in dumpSchedule()
403 for (const SUnit &SU : SUnits) { in schedule()
438 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { in ReleaseSucc()
439 SUnit *SuccSU = SuccEdge->getSUnit(); in ReleaseSucc()
473 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { in ReleaseSuccessors()
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/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.h54 std::vector<SUnit *> Available[IDLast], Pending[IDLast];
55 std::vector<SUnit *> AvailableAlus[AluLast];
56 std::vector<SUnit *> PhysicalRegCopy;
77 SUnit *pickNode(bool &IsTopNode) override;
78 void schedNode(SUnit *SU, bool IsTopNode) override;
79 void releaseTopNode(SUnit *SU) override;
80 void releaseBottomNode(SUnit *SU) override;
86 int getInstKind(SUnit *SU);
88 AluKind getAluKind(SUnit *SU) const;
91 SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
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DR600MachineScheduler.cpp44 void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc, in MoveUnits()
45 std::vector<SUnit *> &QDst) in MoveUnits()
57 SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { in pickNode()
58 SUnit *SU = nullptr; in pickNode()
134 const SUnit &S = DAG->SUnits[i]; in pickNode()
144 void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { in schedNode()
192 void R600SchedStrategy::releaseTopNode(SUnit *SU) { in releaseTopNode()
196 void R600SchedStrategy::releaseBottomNode(SUnit *SU) { in releaseBottomNode()
222 R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { in getAluKind()
296 int R600SchedStrategy::getInstKind(SUnit* SU) { in getInstKind()
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/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp125 std::vector<SUnit*> PendingQueue;
144 std::unique_ptr<SUnit*[]> LiveRegDefs;
145 std::unique_ptr<SUnit*[]> LiveRegGens;
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
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DScheduleDAGFast.cpp49 SmallVector<SUnit *, 16> Queue;
53 void push(SUnit *U) { in push()
57 SUnit *pop() { in pop()
59 SUnit *V = Queue.back(); in pop()
77 std::vector<SUnit*> LiveRegDefs;
88 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
94 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
101 void ScheduleNodeBottomUp(SUnit*, unsigned);
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DResourcePriorityQueue.cpp70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU()
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberRCValPredInSU()
77 SUnit *PredSU = I->getSUnit(); in numberRCValPredInSU()
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU()
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberRCValSuccInSU()
115 SUnit *SuccSU = I->getSUnit(); in numberRCValSuccInSU()
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU()
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU()
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberCtrlPredInSU()
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DScheduleDAGSDNodes.h43 std::vector<SUnit*> Sequence;
76 SUnit *newSUnit(SDNode *N);
81 SUnit *Clone(SUnit *N);
91 void InitNumRegDefsLeft(SUnit *SU);
95 virtual void computeLatency(SUnit *SU);
115 void dumpNode(const SUnit *SU) const override;
119 std::string getGraphNodeLabel(const SUnit *SU) const override;
135 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
175 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
DScheduleDAGVLIW.cpp62 std::vector<SUnit*> PendingQueue;
87 void releaseSucc(SUnit *SU, const SDep &D);
88 void releaseSuccessors(SUnit *SU);
89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { in releaseSucc()
117 SUnit *SuccSU = D.getSUnit(); in releaseSucc()
140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { in releaseSuccessors()
142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { in scheduleNodeTopDown()
186 std::vector<SUnit*> NotReady; in listScheduleTopDown()
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DScheduleDAGSDNodes.cpp68 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) { in newSUnit()
70 const SUnit *Addr = nullptr; in newSUnit()
78 SUnit *SU = &SUnits.back(); in newSUnit()
89 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { in Clone()
90 SUnit *SU = newSUnit(Old->getNode()); in Clone()
328 SmallVector<SUnit*, 8> CallSUnits; in BuildSchedUnits()
343 SUnit *NodeSUnit = newSUnit(NI); in BuildSchedUnits()
406 SUnit *SU = CallSUnits.pop_back_val(); in BuildSchedUnits()
413 SUnit *SrcSU = &SUnits[SrcN->getNodeId()]; in BuildSchedUnits()
427 SUnit *SU = &SUnits[su]; in AddSchedEdges()
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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.h51 std::vector<SUnit*> Packet;
87 bool isResourceAvailable(SUnit *SU);
88 bool reserveResources(SUnit *SU);
115 SUnit *SU;
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
188 SUnit *pickOnlyChoice();
212 SUnit *pickNode(bool &IsTopNode) override;
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DHexagonMachineScheduler.cpp25 SUnit* LastSequentialCall = nullptr; in postprocessDAG()
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { in isResourceAvailable()
68 for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(), in isResourceAvailable()
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { in reserveResources()
156 SmallVector<SUnit*, 8> TopRoots, BotRoots; in schedule()
184 SUnit *SU = SchedImpl->pickNode(IsTopNode); in schedule()
228 void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) { in releaseTopNode()
232 for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in releaseTopNode()
245 void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) { in releaseBottomNode()
251 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseBottomNode()
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DHexagonVLIWPacketizer.h62 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
66 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
80 bool canPromoteToDotCur(const MachineInstr* MI, const SUnit* PacketSU,
88 bool canPromoteToDotNew(const MachineInstr* MI, const SUnit* PacketSU,
91 bool canPromoteToNewValue(const MachineInstr* MI, const SUnit* PacketSU,
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.h28 SmallVector<SUnit *, 7> CurGroup;
31 bool isLoadAfterStore(SUnit *SU);
32 bool isBCTRAfterSet(SUnit *SU);
40 HazardType getHazardType(SUnit *SU, int Stalls) override;
41 bool ShouldPreferAnother(SUnit* SU) override;
42 unsigned PreEmitNoops(SUnit *SU) override;
43 void EmitInstruction(SUnit *SU) override;
79 HazardType getHazardType(SUnit *SU, int Stalls) override;
80 void EmitInstruction(SUnit *SU) override;

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