Searched refs:VREV64 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 152 VREV64, // reverse elements within 64-bit doublewords enumerator
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| D | ARMScheduleSwift.td | 549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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| D | ARMISelLowering.cpp | 1192 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4226 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
5856 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
5919 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
5982 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
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| D | ARMInstrNEON.td | 574 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
6261 // VREV64 : Vector Reverse elements within 64-bit doublewords
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 779 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
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