| /external/llvm/test/CodeGen/X86/ |
| D | vshift-2.ll | 15 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
20 %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
21 %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
36 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
41 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
42 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
43 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
44 %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
61 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
67 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
[all …]
|
| D | vshift-1.ll | 15 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
20 %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
21 %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
37 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
42 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
43 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
44 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
45 %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
61 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
67 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
[all …]
|
| D | vshift-3.ll | 26 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
31 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
32 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
33 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
34 %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
49 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
55 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
56 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
57 %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
58 %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
[all …]
|
| D | vshift-4.ll | 32 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
36 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
42 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
46 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
52 define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
56 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
62 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
67 …%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32…
73 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
78 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
[all …]
|
| D | vshift-5.ll | 10 %amt = load i32, i32* %pamt
11 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
24 %amt = load i32, i32* %pamt
25 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
33 define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
38 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
46 define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
51 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-07.ll | 33 define i64 @f4(i64 %a, i64 %amt) {
37 %shift = ashr i64 %a, %amt
42 define i64 @f5(i64 %a, i64 %amt) {
46 %add = add i64 %amt, 10
52 define i64 @f6(i64 %a, i32 %amt) {
56 %add = add i32 %amt, 10
63 define i64 @f7(i64 %a, i32 %amt) {
67 %add = add i32 %amt, 10
75 define i64 @f8(i64 %a, i64 %amt) {
79 %add = add i64 %amt, 524287
[all …]
|
| D | shift-06.ll | 33 define i64 @f4(i64 %a, i64 %amt) {
37 %shift = lshr i64 %a, %amt
42 define i64 @f5(i64 %a, i64 %amt) {
46 %add = add i64 %amt, 10
52 define i64 @f6(i64 %a, i32 %amt) {
56 %add = add i32 %amt, 10
63 define i64 @f7(i64 %a, i32 %amt) {
67 %add = add i32 %amt, 10
75 define i64 @f8(i64 %a, i64 %amt) {
79 %add = add i64 %amt, 524287
[all …]
|
| D | shift-05.ll | 33 define i64 @f4(i64 %a, i64 %amt) {
37 %shift = shl i64 %a, %amt
42 define i64 @f5(i64 %a, i64 %amt) {
46 %add = add i64 %amt, 10
52 define i64 @f6(i64 %a, i32 %amt) {
56 %add = add i32 %amt, 10
63 define i64 @f7(i64 %a, i32 %amt) {
67 %add = add i32 %amt, 10
75 define i64 @f8(i64 %a, i64 %amt) {
79 %add = add i64 %amt, 524287
[all …]
|
| D | shift-09.ll | 6 define i32 @f1(i32 %a, i32 %b, i32 %amt) {
10 %add = add i32 %amt, 15
16 define i32 @f2(i32 %a, i32 %amt) {
20 %add = add i32 %amt, 15
26 define i32 @f3(i32 %a, i32 %b, i32 %amt) {
30 %add = add i32 %amt, 15
36 define i32 @f4(i32 %a, i32 %amt) {
40 %add = add i32 %amt, 15
46 define i32 @f5(i32 %a, i32 %b, i32 %amt) {
50 %add = add i32 %amt, 15
[all …]
|
| D | shift-08.ll | 39 define i64 @f4(i64 %a, i64 %amt) {
43 %amtb = sub i64 64, %amt
44 %parta = shl i64 %a, %amt
51 define i64 @f5(i64 %a, i64 %amt) {
55 %add = add i64 %amt, 10
64 define i64 @f6(i64 %a, i32 %amt) {
68 %add = add i32 %amt, 10
79 define i64 @f7(i64 %a, i32 %amt) {
83 %add = add i32 %amt, 10
95 define i64 @f8(i64 %a, i64 %amt) {
[all …]
|
| D | shift-04.ll | 39 define i32 @f4(i32 %a, i32 %amt) {
43 %amtb = sub i32 32, %amt
44 %parta = shl i32 %a, %amt
51 define i32 @f5(i32 %a, i32 %amt) {
55 %add = add i32 %amt, 10
64 define i32 @f6(i32 %a, i64 %amt) {
68 %add = add i64 %amt, 10
78 define i32 @f7(i32 %a, i64 %amt) {
82 %add = add i64 %amt, 10
94 define i32 @f8(i32 %a, i32 %amt) {
[all …]
|
| D | shift-01.ll | 33 define i32 @f4(i32 %a, i32 %amt) {
37 %sub = sub i32 %amt, 1
43 define i32 @f5(i32 %a, i32 %amt) {
47 %shift = shl i32 %a, %amt
52 define i32 @f6(i32 %a, i32 %amt) {
56 %add = add i32 %amt, 10
62 define i32 @f7(i32 %a, i64 %amt) {
66 %add = add i64 %amt, 10
74 define i32 @f8(i32 %a, i32 %amt) {
78 %add = add i32 %amt, 4095
[all …]
|
| D | shift-03.ll | 33 define i32 @f4(i32 %a, i32 %amt) {
37 %sub = sub i32 %amt, 1
43 define i32 @f5(i32 %a, i32 %amt) {
47 %shift = ashr i32 %a, %amt
52 define i32 @f6(i32 %a, i32 %amt) {
56 %add = add i32 %amt, 10
62 define i32 @f7(i32 %a, i64 %amt) {
66 %add = add i64 %amt, 10
74 define i32 @f8(i32 %a, i32 %amt) {
78 %add = add i32 %amt, 4095
[all …]
|
| D | shift-02.ll | 33 define i32 @f4(i32 %a, i32 %amt) {
37 %sub = sub i32 %amt, 1
43 define i32 @f5(i32 %a, i32 %amt) {
47 %shift = lshr i32 %a, %amt
52 define i32 @f6(i32 %a, i32 %amt) {
56 %add = add i32 %amt, 10
62 define i32 @f7(i32 %a, i64 %amt) {
66 %add = add i64 %amt, 10
74 define i32 @f8(i32 %a, i32 %amt) {
78 %add = add i32 %amt, 4095
[all …]
|
| /external/valgrind/none/tests/ |
| D | pth_cancel2.c | 26 #define async_cancel_safe_read(fd,buf,amt) \ argument
30 if (read(fd,buf,amt) < 0) \
37 #define async_cancel_safe_write(fd,buf,amt) \ argument
41 if (write(fd,buf,amt) < 0) \
54 int amt=20; in io() local
57 async_cancel_safe_write(*fd2,buf,amt); in io()
58 async_cancel_safe_read(*fd2,buf,amt); in io()
|
| /external/valgrind/none/tests/amd64/ |
| D | shrld.c | 8 ULong amt; variable
172 amt = (ULong)i; in main()
185 amt = (ULong)i; in main()
199 amt = (ULong)i; in main()
213 amt = (ULong)i; in main()
226 amt = (ULong)i; in main()
240 amt = (ULong)i; in main()
|
| /external/dexmaker/src/dx/java/com/android/dx/util/ |
| D | FileUtils.java | 78 int amt = in.read(result, at, length); in readFile() local
79 if (amt == -1) { in readFile()
82 at += amt; in readFile()
83 length -= amt; in readFile()
|
| /external/chromium-trace/catapult/third_party/gsutil/gslib/ |
| D | daisy_chain_wrapper.py | 185 def read(self, amt=None): # pylint: disable=invalid-name argument
187 if self.position == self.src_obj_size or amt == 0:
191 if amt is None or amt > TRANSFER_BUFFER_SIZE:
194 'expected <= %s.' % (amt, TRANSFER_BUFFER_SIZE))
216 if data_len > amt:
219 '%s, expected size %s.' % (data_len, amt))
|
| /external/llvm/test/CodeGen/NVPTX/ |
| D | shift-parts.ll | 15 %amt = load i128, i128* %amtptr
17 %val0 = shl i128 %a, %amt
33 %amt = load i128, i128* %amtptr
35 %val0 = ashr i128 %a, %amt
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
34 "ret{l}\t$amt",
35 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
38 "ret{q}\t$amt",
39 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
42 "ret{w}\t$amt",
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
[all …]
|
| /external/smali/util/src/main/java/org/jf/util/ |
| D | TwoColumnOutput.java | 149 private static void writeSpaces(Writer out, int amt) throws IOException { in writeSpaces() argument
150 while (amt > 0) { in writeSpaces()
152 amt--; in writeSpaces()
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | 2006-11-10-ashr-miscompile.ll | 4 define i32 @test(i8 %amt) {
5 %shift.upgrd.1 = zext i8 %amt to i32 ; <i32> [#uses=1]
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrCall.td | 22 def ADJCALLSTACKDOWN : I<(outs), (ins i32imm:$amt),
23 [(WebAssemblycallseq_start timm:$amt)]>;
24 def ADJCALLSTACKUP : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
25 [(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
|
| /external/jarjar/src/main/com/tonicsystems/jarjar/util/ |
| D | IoUtil.java | 33 int amt = is.read(buf); in pipe() local
34 if (amt < 0) in pipe()
36 out.write(buf, 0, amt); in pipe()
|
| /external/tcpdump/ |
| D | print-ripng.c | 114 register u_int amt; in ripng_print() local
121 amt = ndo->ndo_snapend - dat; in ripng_print()
122 i = min(length, amt); in ripng_print()
|