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Searched refs:subc (Results 1 – 24 of 24) sorted by relevance

/external/mesa3d/src/gallium/drivers/nvc0/
Dnvc0_winsys.h69 NVC0_FIFO_PKHDR_SQ(int subc, int mthd, unsigned size) in NVC0_FIFO_PKHDR_SQ() argument
71 return 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2); in NVC0_FIFO_PKHDR_SQ()
75 NVC0_FIFO_PKHDR_NI(int subc, int mthd, unsigned size) in NVC0_FIFO_PKHDR_NI() argument
77 return 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2); in NVC0_FIFO_PKHDR_NI()
81 NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint8_t data) in NVC0_FIFO_PKHDR_IL() argument
83 return 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2); in NVC0_FIFO_PKHDR_IL()
87 NVC0_FIFO_PKHDR_1I(int subc, int mthd, unsigned size) in NVC0_FIFO_PKHDR_1I() argument
89 return 0xa0000000 | (size << 16) | (subc << 13) | (mthd >> 2); in NVC0_FIFO_PKHDR_1I()
107 BEGIN_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) in BEGIN_NVC0() argument
112 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(subc, mthd, size)); in BEGIN_NVC0()
[all …]
/external/mesa3d/src/gallium/drivers/nv30/
Dnv30_winsys.h50 PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHDl() argument
53 nouveau_bufctx_mthd(bufctx(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHDl()
59 PUSH_MTHDo(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHDo() argument
62 nouveau_bufctx_mthd(bufctx(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHDo()
71 PUSH_MTHDs(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHDs() argument
75 nouveau_bufctx_mthd(bufctx(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHDs()
84 PUSH_MTHD(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHD() argument
89 nouveau_bufctx_mthd(bufctx(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHD()
103 PUSH_RESRC(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_RESRC() argument
107 PUSH_MTHD(push, subc, mthd, bin, r->bo, r->offset + data, in PUSH_RESRC()
[all …]
/external/mesa3d/src/gallium/drivers/nv50/
Dnv50_winsys.h65 NV50_FIFO_PKHDR(int subc, int mthd, unsigned size) in NV50_FIFO_PKHDR() argument
67 return 0x00000000 | (size << 18) | (subc << 13) | mthd; in NV50_FIFO_PKHDR()
71 NV50_FIFO_PKHDR_NI(int subc, int mthd, unsigned size) in NV50_FIFO_PKHDR_NI() argument
73 return 0x40000000 | (size << 18) | (subc << 13) | mthd; in NV50_FIFO_PKHDR_NI()
77 NV50_FIFO_PKHDR_L(int subc, int mthd) in NV50_FIFO_PKHDR_L() argument
79 return 0x00030000 | (subc << 13) | mthd; in NV50_FIFO_PKHDR_L()
97 BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) in BEGIN_NV04() argument
102 PUSH_DATA (push, NV50_FIFO_PKHDR(subc, mthd, size)); in BEGIN_NV04()
106 BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) in BEGIN_NI04() argument
111 PUSH_DATA (push, NV50_FIFO_PKHDR_NI(subc, mthd, size)); in BEGIN_NI04()
[all …]
/external/mesa3d/src/mesa/drivers/dri/nouveau/
Dnouveau_local.h102 PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHDl() argument
105 nouveau_bufctx_mthd(BUFCTX(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHDl()
111 PUSH_MTHDs(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHDs() argument
115 nouveau_bufctx_mthd(BUFCTX(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHDs()
125 PUSH_MTHD(struct nouveau_pushbuf *push, int subc, int mthd, int bin, in PUSH_MTHD() argument
129 nouveau_bufctx_mthd(BUFCTX(push), bin, (1 << 18) | (subc << 13) | mthd, in PUSH_MTHD()
146 BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, int size) in BEGIN_NV04() argument
149 PUSH_DATA (push, 0x00000000 | (size << 18) | (subc << 13) | mthd); in BEGIN_NV04()
153 BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, int size) in BEGIN_NI04() argument
156 PUSH_DATA (push, 0x40000000 | (size << 18) | (subc << 13) | mthd); in BEGIN_NI04()
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/
Dnouveau_video.h58 NV04_FIFO_PKHDR(int subc, int mthd, unsigned size) in NV04_FIFO_PKHDR() argument
60 return 0x00000000 | (size << 18) | (subc << 13) | mthd; in NV04_FIFO_PKHDR()
64 NV04_FIFO_PKHDR_NI(int subc, int mthd, unsigned size) in NV04_FIFO_PKHDR_NI() argument
66 return 0x40000000 | (size << 18) | (subc << 13) | mthd; in NV04_FIFO_PKHDR_NI()
70 BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) in BEGIN_NV04() argument
73 PUSH_DATA (push, NV04_FIFO_PKHDR(subc, mthd, size)); in BEGIN_NV04()
77 BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) in BEGIN_NI04() argument
80 PUSH_DATA (push, NV04_FIFO_PKHDR_NI(subc, mthd, size)); in BEGIN_NI04()
84 PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, in PUSH_MTHDl() argument
88 nouveau_bufctx_mthd(ctx, bin, NV04_FIFO_PKHDR(subc, mthd, 1), in PUSH_MTHDl()
Dnouveau_statebuf.h23 static INLINE uint32_t sb_header(unsigned subc, unsigned mthd, unsigned size) in sb_header() argument
25 return (size << 18) | (subc << 13) | mthd; in sb_header()
/external/llvm/test/CodeGen/ARM/
D2011-08-29-SchedCycle.ll3 ; When a i64 sub is expanded to subc + sube.
6 ; \ subc
16 ; subc
24 ; However since subc and sube are "glued" together, this ends up being a
25 ; cycle when the scheduler combine subc and sube as a single scheduling
30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
/external/antlr/antlr-3.4/runtime/JavaScript/src/org/
Dantlr.js372 extend: function(subc, superc, overrides) { argument
373 if (!superc||!subc) {
379 subc.prototype=new F(); class
380 subc.prototype.constructor=subc;
381 subc.superclass=superc.prototype;
388 subc.prototype[i]=overrides[i];
391 org.antlr.lang._IEEnumFix(subc.prototype, overrides);
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td869 "subc.b\t{$src2, $dst}",
874 "subc.w\t{$src2, $dst}",
880 "subc.b\t{$src2, $dst}",
885 "subc.w\t{$src2, $dst}",
891 "subc.b\t{$src2, $dst}",
896 "subc.w\t{$src2, $dst}",
903 "subc.b\t{$src, $dst}",
908 "subc.w\t{$src, $dst}",
914 "subc.b\t{$src, $dst}",
919 "subc.w\t{$src, $dst}",
[all …]
/external/llvm/test/CodeGen/PowerPC/
Doptcmp.ll143 %subc = call i64 @llvm.ctpop.i64(i64 %sub)
144 store i64 %subc, i64* %c, align 4
145 %cmp = icmp sgt i64 %subc, 0
/external/llvm/test/MC/Sparc/
Dsparcv9-instructions.s15 ! V8-NEXT: subc %g2, %g1, %g3
17 subc %g2, %g1, %g3
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td795 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
797 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
800 // subc because we prefer addc for constants.
805 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
806 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
807 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
809 defm : ZXB<subc, GR64, SLGFR>;
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td322 def SubCCV4I32 : VecBinaryOp<V4AsmStr<"sub.cc.s32">, subc, V4I32Regs,
324 def SubCCV2I32 : VecBinaryOp<V2AsmStr<"sub.cc.s32">, subc, V2I32Regs,
330 def SubCCCV4I32 : VecBinaryOp<V4AsmStr<"subc.cc.s32">, sube, V4I32Regs,
332 def SubCCCV2I32 : VecBinaryOp<V2AsmStr<"subc.cc.s32">, sube, V2I32Regs,
DNVPTXInstrInfo.td400 defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
403 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td441 def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
DSparcInstrInfo.td603 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-ext.s3012 # CHECK-BE: subc 2, 3, 4 # encoding: [0x7c,0x44,0x18,0x10]
3013 # CHECK-LE: subc 2, 3, 4 # encoding: [0x10,0x18,0x44,0x7c]
3014 subc 2, 3, 4
3015 # CHECK-BE: subc. 2, 3, 4 # encoding: [0x7c,0x44,0x18,0x11]
3016 # CHECK-LE: subc. 2, 3, 4 # encoding: [0x11,0x18,0x44,0x7c]
3017 subc. 2, 3, 4
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td491 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
494 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
DPPCInstrInfo.td1899 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2408 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
3794 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3795 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td533 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
DMips16InstrInfo.td1412 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
DMipsInstrInfo.td2058 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td390 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td1338 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),