1 /*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "context_x86.h"
18
19 #include "base/bit_utils.h"
20 #include "quick/quick_method_frame_info.h"
21
22 namespace art {
23 namespace x86 {
24
25 static constexpr uintptr_t gZero = 0;
26
Reset()27 void X86Context::Reset() {
28 std::fill_n(gprs_, arraysize(gprs_), nullptr);
29 std::fill_n(fprs_, arraysize(fprs_), nullptr);
30 gprs_[ESP] = &esp_;
31 gprs_[EAX] = &arg0_;
32 // Initialize registers with easy to spot debug values.
33 esp_ = X86Context::kBadGprBase + ESP;
34 eip_ = X86Context::kBadGprBase + kNumberOfCpuRegisters;
35 arg0_ = 0;
36 }
37
FillCalleeSaves(uint8_t * frame,const QuickMethodFrameInfo & frame_info)38 void X86Context::FillCalleeSaves(uint8_t* frame, const QuickMethodFrameInfo& frame_info) {
39 int spill_pos = 0;
40
41 // Core registers come first, from the highest down to the lowest.
42 uint32_t core_regs =
43 frame_info.CoreSpillMask() & ~(static_cast<uint32_t>(-1) << kNumberOfCpuRegisters);
44 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
45 for (uint32_t core_reg : HighToLowBits(core_regs)) {
46 gprs_[core_reg] = CalleeSaveAddress(frame, spill_pos, frame_info.FrameSizeInBytes());
47 ++spill_pos;
48 }
49 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) - 1);
50
51 // FP registers come second, from the highest down to the lowest.
52 uint32_t fp_regs = frame_info.FpSpillMask();
53 DCHECK_EQ(0u, fp_regs & (static_cast<uint32_t>(-1) << kNumberOfFloatRegisters));
54 for (uint32_t fp_reg : HighToLowBits(fp_regs)) {
55 // Two void* per XMM register.
56 fprs_[2 * fp_reg] = reinterpret_cast<uint32_t*>(
57 CalleeSaveAddress(frame, spill_pos + 1, frame_info.FrameSizeInBytes()));
58 fprs_[2 * fp_reg + 1] = reinterpret_cast<uint32_t*>(
59 CalleeSaveAddress(frame, spill_pos, frame_info.FrameSizeInBytes()));
60 spill_pos += 2;
61 }
62 DCHECK_EQ(spill_pos,
63 POPCOUNT(frame_info.CoreSpillMask()) - 1 + 2 * POPCOUNT(frame_info.FpSpillMask()));
64 }
65
SmashCallerSaves()66 void X86Context::SmashCallerSaves() {
67 // This needs to be 0 because we want a null/zero return value.
68 gprs_[EAX] = const_cast<uintptr_t*>(&gZero);
69 gprs_[EDX] = const_cast<uintptr_t*>(&gZero);
70 gprs_[ECX] = nullptr;
71 gprs_[EBX] = nullptr;
72 memset(&fprs_[0], '\0', sizeof(fprs_));
73 }
74
SetGPR(uint32_t reg,uintptr_t value)75 void X86Context::SetGPR(uint32_t reg, uintptr_t value) {
76 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
77 DCHECK(IsAccessibleGPR(reg));
78 CHECK_NE(gprs_[reg], &gZero);
79 *gprs_[reg] = value;
80 }
81
SetFPR(uint32_t reg,uintptr_t value)82 void X86Context::SetFPR(uint32_t reg, uintptr_t value) {
83 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters));
84 DCHECK(IsAccessibleFPR(reg));
85 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero));
86 *fprs_[reg] = value;
87 }
88
DoLongJump()89 void X86Context::DoLongJump() {
90 #if defined(__i386__)
91 // Array of GPR values, filled from the context backward for the long jump pop. We add a slot at
92 // the top for the stack pointer that doesn't get popped in a pop-all.
93 volatile uintptr_t gprs[kNumberOfCpuRegisters + 1];
94 for (size_t i = 0; i < kNumberOfCpuRegisters; ++i) {
95 gprs[kNumberOfCpuRegisters - i - 1] = gprs_[i] != nullptr ? *gprs_[i] : X86Context::kBadGprBase + i;
96 }
97 uint32_t fprs[kNumberOfFloatRegisters];
98 for (size_t i = 0; i < kNumberOfFloatRegisters; ++i) {
99 fprs[i] = fprs_[i] != nullptr ? *fprs_[i] : X86Context::kBadFprBase + i;
100 }
101 // We want to load the stack pointer one slot below so that the ret will pop eip.
102 uintptr_t esp = gprs[kNumberOfCpuRegisters - ESP - 1] - sizeof(intptr_t);
103 gprs[kNumberOfCpuRegisters] = esp;
104 *(reinterpret_cast<uintptr_t*>(esp)) = eip_;
105 __asm__ __volatile__(
106 "movl %1, %%ebx\n\t" // Address base of FPRs.
107 "movsd 0(%%ebx), %%xmm0\n\t" // Load up XMM0-XMM7.
108 "movsd 8(%%ebx), %%xmm1\n\t"
109 "movsd 16(%%ebx), %%xmm2\n\t"
110 "movsd 24(%%ebx), %%xmm3\n\t"
111 "movsd 32(%%ebx), %%xmm4\n\t"
112 "movsd 40(%%ebx), %%xmm5\n\t"
113 "movsd 48(%%ebx), %%xmm6\n\t"
114 "movsd 56(%%ebx), %%xmm7\n\t"
115 "movl %0, %%esp\n\t" // ESP points to gprs.
116 "popal\n\t" // Load all registers except ESP and EIP with values in gprs.
117 "popl %%esp\n\t" // Load stack pointer.
118 "ret\n\t" // From higher in the stack pop eip.
119 : // output.
120 : "g"(&gprs[0]), "g"(&fprs[0]) // input.
121 :); // clobber.
122 #else
123 UNIMPLEMENTED(FATAL);
124 #endif
125 UNREACHABLE();
126 }
127
128 } // namespace x86
129 } // namespace art
130