1 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Thumb2InstrInfo.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Support/CommandLine.h"
24
25 using namespace llvm;
26
27 static cl::opt<bool>
28 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
29 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
30 cl::init(false));
31
Thumb2InstrInfo(const ARMSubtarget & STI)32 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI() {}
34
35 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
getNoopForMachoTarget(MCInst & NopInst) const36 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
37 NopInst.setOpcode(ARM::tHINT);
38 NopInst.addOperand(MCOperand::createImm(0));
39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
40 NopInst.addOperand(MCOperand::createReg(0));
41 }
42
getUnindexedOpcode(unsigned Opc) const43 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
44 // FIXME
45 return 0;
46 }
47
48 void
ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,MachineBasicBlock * NewDest) const49 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
50 MachineBasicBlock *NewDest) const {
51 MachineBasicBlock *MBB = Tail->getParent();
52 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
53 if (!AFI->hasITBlocks()) {
54 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
55 return;
56 }
57
58 // If the first instruction of Tail is predicated, we may have to update
59 // the IT instruction.
60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
62 MachineBasicBlock::iterator MBBI = Tail;
63 if (CC != ARMCC::AL)
64 // Expecting at least the t2IT instruction before it.
65 --MBBI;
66
67 // Actually replace the tail.
68 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
69
70 // Fix up IT.
71 if (CC != ARMCC::AL) {
72 MachineBasicBlock::iterator E = MBB->begin();
73 unsigned Count = 4; // At most 4 instructions in an IT block.
74 while (Count && MBBI != E) {
75 if (MBBI->isDebugValue()) {
76 --MBBI;
77 continue;
78 }
79 if (MBBI->getOpcode() == ARM::t2IT) {
80 unsigned Mask = MBBI->getOperand(1).getImm();
81 if (Count == 4)
82 MBBI->eraseFromParent();
83 else {
84 unsigned MaskOn = 1 << Count;
85 unsigned MaskOff = ~(MaskOn - 1);
86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
87 }
88 return;
89 }
90 --MBBI;
91 --Count;
92 }
93
94 // Ctrl flow can reach here if branch folding is run before IT block
95 // formation pass.
96 }
97 }
98
99 bool
isLegalToSplitMBBAt(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI) const100 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MBBI) const {
102 while (MBBI->isDebugValue()) {
103 ++MBBI;
104 if (MBBI == MBB.end())
105 return false;
106 }
107
108 unsigned PredReg = 0;
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
110 }
111
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const112 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator I, DebugLoc DL,
114 unsigned DestReg, unsigned SrcReg,
115 bool KillSrc) const {
116 // Handle SPR, DPR, and QPR copies.
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
119
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
121 .addReg(SrcReg, getKillRegState(KillSrc)));
122 }
123
124 void Thumb2InstrInfo::
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126 unsigned SrcReg, bool isKill, int FI,
127 const TargetRegisterClass *RC,
128 const TargetRegisterInfo *TRI) const {
129 DebugLoc DL;
130 if (I != MBB.end()) DL = I->getDebugLoc();
131
132 MachineFunction &MF = *MBB.getParent();
133 MachineFrameInfo &MFI = *MF.getFrameInfo();
134 MachineMemOperand *MMO = MF.getMachineMemOperand(
135 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
136 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
137
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
140 RC == &ARM::GPRnopcRegClass) {
141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
142 .addReg(SrcReg, getKillRegState(isKill))
143 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
144 return;
145 }
146
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
148 // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
149 // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
150 // otherwise).
151 MachineRegisterInfo *MRI = &MF.getRegInfo();
152 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
153
154 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
155 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
156 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
157 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
158 AddDefaultPred(MIB);
159 return;
160 }
161
162 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
163 }
164
165 void Thumb2InstrInfo::
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const166 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
167 unsigned DestReg, int FI,
168 const TargetRegisterClass *RC,
169 const TargetRegisterInfo *TRI) const {
170 MachineFunction &MF = *MBB.getParent();
171 MachineFrameInfo &MFI = *MF.getFrameInfo();
172 MachineMemOperand *MMO = MF.getMachineMemOperand(
173 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
174 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
175 DebugLoc DL;
176 if (I != MBB.end()) DL = I->getDebugLoc();
177
178 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
179 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
180 RC == &ARM::GPRnopcRegClass) {
181 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
182 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
183 return;
184 }
185
186 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
187 // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
188 // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
189 // otherwise).
190 MachineRegisterInfo *MRI = &MF.getRegInfo();
191 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
192
193 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
194 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
195 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
196 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
197 AddDefaultPred(MIB);
198
199 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
200 MIB.addReg(DestReg, RegState::ImplicitDefine);
201 return;
202 }
203
204 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
205 }
206
207 void
expandLoadStackGuard(MachineBasicBlock::iterator MI,Reloc::Model RM) const208 Thumb2InstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
209 Reloc::Model RM) const {
210 if (RM == Reloc::PIC_)
211 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12, RM);
212 else
213 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12, RM);
214 }
215
emitT2RegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,DebugLoc dl,unsigned DestReg,unsigned BaseReg,int NumBytes,ARMCC::CondCodes Pred,unsigned PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags)216 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
218 unsigned DestReg, unsigned BaseReg, int NumBytes,
219 ARMCC::CondCodes Pred, unsigned PredReg,
220 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
221 if (NumBytes == 0 && DestReg != BaseReg) {
222 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
223 .addReg(BaseReg, RegState::Kill)
224 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
225 return;
226 }
227
228 bool isSub = NumBytes < 0;
229 if (isSub) NumBytes = -NumBytes;
230
231 // If profitable, use a movw or movt to materialize the offset.
232 // FIXME: Use the scavenger to grab a scratch register.
233 if (DestReg != ARM::SP && DestReg != BaseReg &&
234 NumBytes >= 4096 &&
235 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
236 bool Fits = false;
237 if (NumBytes < 65536) {
238 // Use a movw to materialize the 16-bit constant.
239 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
240 .addImm(NumBytes)
241 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
242 Fits = true;
243 } else if ((NumBytes & 0xffff) == 0) {
244 // Use a movt to materialize the 32-bit constant.
245 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
246 .addReg(DestReg)
247 .addImm(NumBytes >> 16)
248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
249 Fits = true;
250 }
251
252 if (Fits) {
253 if (isSub) {
254 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
255 .addReg(BaseReg)
256 .addReg(DestReg, RegState::Kill)
257 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
258 .setMIFlags(MIFlags);
259 } else {
260 // Here we know that DestReg is not SP but we do not
261 // know anything about BaseReg. t2ADDrr is an invalid
262 // instruction is SP is used as the second argument, but
263 // is fine if SP is the first argument. To be sure we
264 // do not generate invalid encoding, put BaseReg first.
265 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
266 .addReg(BaseReg)
267 .addReg(DestReg, RegState::Kill)
268 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
269 .setMIFlags(MIFlags);
270 }
271 return;
272 }
273 }
274
275 while (NumBytes) {
276 unsigned ThisVal = NumBytes;
277 unsigned Opc = 0;
278 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
279 // mov sp, rn. Note t2MOVr cannot be used.
280 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
281 .addReg(BaseReg).setMIFlags(MIFlags));
282 BaseReg = ARM::SP;
283 continue;
284 }
285
286 bool HasCCOut = true;
287 if (BaseReg == ARM::SP) {
288 // sub sp, sp, #imm7
289 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
290 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
291 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
292 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
293 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
294 NumBytes = 0;
295 continue;
296 }
297
298 // sub rd, sp, so_imm
299 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
300 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
301 NumBytes = 0;
302 } else {
303 // FIXME: Move this to ARMAddressingModes.h?
304 unsigned RotAmt = countLeadingZeros(ThisVal);
305 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
306 NumBytes &= ~ThisVal;
307 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
308 "Bit extraction didn't work?");
309 }
310 } else {
311 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
312 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
313 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
314 NumBytes = 0;
315 } else if (ThisVal < 4096) {
316 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
317 HasCCOut = false;
318 NumBytes = 0;
319 } else {
320 // FIXME: Move this to ARMAddressingModes.h?
321 unsigned RotAmt = countLeadingZeros(ThisVal);
322 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
323 NumBytes &= ~ThisVal;
324 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
325 "Bit extraction didn't work?");
326 }
327 }
328
329 // Build the new ADD / SUB.
330 MachineInstrBuilder MIB =
331 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
332 .addReg(BaseReg, RegState::Kill)
333 .addImm(ThisVal)).setMIFlags(MIFlags);
334 if (HasCCOut)
335 AddDefaultCC(MIB);
336
337 BaseReg = DestReg;
338 }
339 }
340
341 static unsigned
negativeOffsetOpcode(unsigned opcode)342 negativeOffsetOpcode(unsigned opcode)
343 {
344 switch (opcode) {
345 case ARM::t2LDRi12: return ARM::t2LDRi8;
346 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
347 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
348 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
349 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
350 case ARM::t2STRi12: return ARM::t2STRi8;
351 case ARM::t2STRBi12: return ARM::t2STRBi8;
352 case ARM::t2STRHi12: return ARM::t2STRHi8;
353 case ARM::t2PLDi12: return ARM::t2PLDi8;
354
355 case ARM::t2LDRi8:
356 case ARM::t2LDRHi8:
357 case ARM::t2LDRBi8:
358 case ARM::t2LDRSHi8:
359 case ARM::t2LDRSBi8:
360 case ARM::t2STRi8:
361 case ARM::t2STRBi8:
362 case ARM::t2STRHi8:
363 case ARM::t2PLDi8:
364 return opcode;
365
366 default:
367 break;
368 }
369
370 return 0;
371 }
372
373 static unsigned
positiveOffsetOpcode(unsigned opcode)374 positiveOffsetOpcode(unsigned opcode)
375 {
376 switch (opcode) {
377 case ARM::t2LDRi8: return ARM::t2LDRi12;
378 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
379 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
380 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
381 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
382 case ARM::t2STRi8: return ARM::t2STRi12;
383 case ARM::t2STRBi8: return ARM::t2STRBi12;
384 case ARM::t2STRHi8: return ARM::t2STRHi12;
385 case ARM::t2PLDi8: return ARM::t2PLDi12;
386
387 case ARM::t2LDRi12:
388 case ARM::t2LDRHi12:
389 case ARM::t2LDRBi12:
390 case ARM::t2LDRSHi12:
391 case ARM::t2LDRSBi12:
392 case ARM::t2STRi12:
393 case ARM::t2STRBi12:
394 case ARM::t2STRHi12:
395 case ARM::t2PLDi12:
396 return opcode;
397
398 default:
399 break;
400 }
401
402 return 0;
403 }
404
405 static unsigned
immediateOffsetOpcode(unsigned opcode)406 immediateOffsetOpcode(unsigned opcode)
407 {
408 switch (opcode) {
409 case ARM::t2LDRs: return ARM::t2LDRi12;
410 case ARM::t2LDRHs: return ARM::t2LDRHi12;
411 case ARM::t2LDRBs: return ARM::t2LDRBi12;
412 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
413 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
414 case ARM::t2STRs: return ARM::t2STRi12;
415 case ARM::t2STRBs: return ARM::t2STRBi12;
416 case ARM::t2STRHs: return ARM::t2STRHi12;
417 case ARM::t2PLDs: return ARM::t2PLDi12;
418
419 case ARM::t2LDRi12:
420 case ARM::t2LDRHi12:
421 case ARM::t2LDRBi12:
422 case ARM::t2LDRSHi12:
423 case ARM::t2LDRSBi12:
424 case ARM::t2STRi12:
425 case ARM::t2STRBi12:
426 case ARM::t2STRHi12:
427 case ARM::t2PLDi12:
428 case ARM::t2LDRi8:
429 case ARM::t2LDRHi8:
430 case ARM::t2LDRBi8:
431 case ARM::t2LDRSHi8:
432 case ARM::t2LDRSBi8:
433 case ARM::t2STRi8:
434 case ARM::t2STRBi8:
435 case ARM::t2STRHi8:
436 case ARM::t2PLDi8:
437 return opcode;
438
439 default:
440 break;
441 }
442
443 return 0;
444 }
445
rewriteT2FrameIndex(MachineInstr & MI,unsigned FrameRegIdx,unsigned FrameReg,int & Offset,const ARMBaseInstrInfo & TII)446 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
447 unsigned FrameReg, int &Offset,
448 const ARMBaseInstrInfo &TII) {
449 unsigned Opcode = MI.getOpcode();
450 const MCInstrDesc &Desc = MI.getDesc();
451 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
452 bool isSub = false;
453
454 // Memory operands in inline assembly always use AddrModeT2_i12.
455 if (Opcode == ARM::INLINEASM)
456 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
457
458 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
459 Offset += MI.getOperand(FrameRegIdx+1).getImm();
460
461 unsigned PredReg;
462 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
463 // Turn it into a move.
464 MI.setDesc(TII.get(ARM::tMOVr));
465 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
466 // Remove offset and remaining explicit predicate operands.
467 do MI.RemoveOperand(FrameRegIdx+1);
468 while (MI.getNumOperands() > FrameRegIdx+1);
469 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
470 AddDefaultPred(MIB);
471 return true;
472 }
473
474 bool HasCCOut = Opcode != ARM::t2ADDri12;
475
476 if (Offset < 0) {
477 Offset = -Offset;
478 isSub = true;
479 MI.setDesc(TII.get(ARM::t2SUBri));
480 } else {
481 MI.setDesc(TII.get(ARM::t2ADDri));
482 }
483
484 // Common case: small offset, fits into instruction.
485 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
486 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
487 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
488 // Add cc_out operand if the original instruction did not have one.
489 if (!HasCCOut)
490 MI.addOperand(MachineOperand::CreateReg(0, false));
491 Offset = 0;
492 return true;
493 }
494 // Another common case: imm12.
495 if (Offset < 4096 &&
496 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
497 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
498 MI.setDesc(TII.get(NewOpc));
499 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
500 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
501 // Remove the cc_out operand.
502 if (HasCCOut)
503 MI.RemoveOperand(MI.getNumOperands()-1);
504 Offset = 0;
505 return true;
506 }
507
508 // Otherwise, extract 8 adjacent bits from the immediate into this
509 // t2ADDri/t2SUBri.
510 unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
511 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
512
513 // We will handle these bits from offset, clear them.
514 Offset &= ~ThisImmVal;
515
516 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
517 "Bit extraction didn't work?");
518 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
519 // Add cc_out operand if the original instruction did not have one.
520 if (!HasCCOut)
521 MI.addOperand(MachineOperand::CreateReg(0, false));
522
523 } else {
524
525 // AddrMode4 and AddrMode6 cannot handle any offset.
526 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
527 return false;
528
529 // AddrModeT2_so cannot handle any offset. If there is no offset
530 // register then we change to an immediate version.
531 unsigned NewOpc = Opcode;
532 if (AddrMode == ARMII::AddrModeT2_so) {
533 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
534 if (OffsetReg != 0) {
535 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
536 return Offset == 0;
537 }
538
539 MI.RemoveOperand(FrameRegIdx+1);
540 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
541 NewOpc = immediateOffsetOpcode(Opcode);
542 AddrMode = ARMII::AddrModeT2_i12;
543 }
544
545 unsigned NumBits = 0;
546 unsigned Scale = 1;
547 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
548 // i8 supports only negative, and i12 supports only positive, so
549 // based on Offset sign convert Opcode to the appropriate
550 // instruction
551 Offset += MI.getOperand(FrameRegIdx+1).getImm();
552 if (Offset < 0) {
553 NewOpc = negativeOffsetOpcode(Opcode);
554 NumBits = 8;
555 isSub = true;
556 Offset = -Offset;
557 } else {
558 NewOpc = positiveOffsetOpcode(Opcode);
559 NumBits = 12;
560 }
561 } else if (AddrMode == ARMII::AddrMode5) {
562 // VFP address mode.
563 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
564 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
565 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
566 InstrOffs *= -1;
567 NumBits = 8;
568 Scale = 4;
569 Offset += InstrOffs * 4;
570 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
571 if (Offset < 0) {
572 Offset = -Offset;
573 isSub = true;
574 }
575 } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
576 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
577 NumBits = 10; // 8 bits scaled by 4
578 // MCInst operand expects already scaled value.
579 Scale = 1;
580 assert((Offset & 3) == 0 && "Can't encode this offset!");
581 } else {
582 llvm_unreachable("Unsupported addressing mode!");
583 }
584
585 if (NewOpc != Opcode)
586 MI.setDesc(TII.get(NewOpc));
587
588 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
589
590 // Attempt to fold address computation
591 // Common case: small offset, fits into instruction.
592 int ImmedOffset = Offset / Scale;
593 unsigned Mask = (1 << NumBits) - 1;
594 if ((unsigned)Offset <= Mask * Scale) {
595 // Replace the FrameIndex with fp/sp
596 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
597 if (isSub) {
598 if (AddrMode == ARMII::AddrMode5)
599 // FIXME: Not consistent.
600 ImmedOffset |= 1 << NumBits;
601 else
602 ImmedOffset = -ImmedOffset;
603 }
604 ImmOp.ChangeToImmediate(ImmedOffset);
605 Offset = 0;
606 return true;
607 }
608
609 // Otherwise, offset doesn't fit. Pull in what we can to simplify
610 ImmedOffset = ImmedOffset & Mask;
611 if (isSub) {
612 if (AddrMode == ARMII::AddrMode5)
613 // FIXME: Not consistent.
614 ImmedOffset |= 1 << NumBits;
615 else {
616 ImmedOffset = -ImmedOffset;
617 if (ImmedOffset == 0)
618 // Change the opcode back if the encoded offset is zero.
619 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
620 }
621 }
622 ImmOp.ChangeToImmediate(ImmedOffset);
623 Offset &= ~(Mask*Scale);
624 }
625
626 Offset = (isSub) ? -Offset : Offset;
627 return Offset == 0;
628 }
629
630 ARMCC::CondCodes
getITInstrPredicate(const MachineInstr * MI,unsigned & PredReg)631 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
632 unsigned Opc = MI->getOpcode();
633 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
634 return ARMCC::AL;
635 return getInstrPredicate(MI, PredReg);
636 }
637