1VIXL Change Log 2=============== 3 4* 1.12 5 + Bug fixes for toolchain compatibility. 6 7* 1.11 8 + Fix bug in simulation of add with carry. 9 + Fix use-after-free bug in Literal handling. 10 + Build system updates for Android. 11 + Add option to run test.py under Valgrind. 12 + Other small bug fixes and improvements. 13 14* 1.10 15 + Improved support for externally managed literals. 16 + Reworked build and test infrastructure. 17 + Other small bug fixes and improvements. 18 19* 1.9 20 + Improved compatibility with Android build system. 21 + Improved compatibility with Clang toolchain. 22 + Added support for `umulh` instruction. 23 + Added support for `fcmpe` and `fccmpe` instructions. 24 + Other small bug fixes and improvements. 25 26* 1.8 27 + Complete NEON instruction set support. 28 + Support long branches using veneers. 29 + Improved handling of literal pools. 30 + Support some `ic` and `dc` cache op instructions. 31 + Support CRC32 instructions. 32 + Support half-precision floating point instructions. 33 + MacroAssembler support for `bfm`, `ubfm` and `sbfm`. 34 + Other small bug fixes and improvements. 35 36* 1.7 37 + Added support for `prfm` prefetch instructions. 38 + Added support for all `frint` instruction variants. 39 + Add support for disassembling as an offset from a given address. 40 + Fixed the disassembly of `movz` and `movn`. 41 + Provide static helpers for immediate generation. 42 + Provide helpers to create CPURegList from list unions or intersections. 43 + Improved register value tracing. 44 + Multithreading test fixes. 45 + Other small bug fixes and build system improvements. 46 47* 1.6 48 + Make literal pool management the responsibility of the macro assembler. 49 + Move code buffer management out of the Assembler. 50 + Support `ldrsw` for literals. 51 + Support binding a label to a specific offset. 52 + Add macro assembler support for load/store pair with arbitrary offset. 53 + Support Peek and Poke for CPURegLists. 54 + Fix disassembly of branch targets. 55 + Fix Decoder visitor insertion order. 56 + Separate Decoder visitors into const and non-const variants. 57 + Fix simulator for branches to tagged addresses. 58 + Add a VIM YouCompleteMe configuration file. 59 + Other small bug fixes and build system improvements. 60 61* 1.5 62 + Tagged pointer support. 63 + Implement support for exclusive access instructions. 64 + Implement support for `adrp` instruction. 65 + Faster code for logical immediate identification. 66 + Generate better code for immediates passed to shift-capable instructions. 67 + Allow explicit use of unscaled-offset loads and stores. 68 + Build and test infrastructure improvements. 69 + Corrected computation of cache line size. 70 + Fix simulation of `extr` instruction. 71 + Fixed a bug when moving kWMinInt to a register. 72 + Other small bug fixes. 73 74* 1.4 75 + Added support for `frintm`. 76 + Fixed simulation of `frintn` and `frinta` for corner cases. 77 + Added more tests for floating point instruction simulation. 78 + Modified `CalleeSave()` and `CalleeRestore()` to push general purpose 79 registers before floating point registers on the stack. 80 + Fixed Printf for mixed argument types, and use on real hardware. 81 + Improved compatibility with some 32-bit compilers. 82 83* 1.3 84 + Address inaccuracies in the simulated floating point instructions. 85 + Implement Default-NaN floating point mode. 86 + Introduce `UseScratchRegisterScope` for controlling the use of temporary 87 registers. 88 + Enable building VIXL on 32-bit hosts. 89 + Other small bug fixes and improvements. 90 91* 1.2 92 + Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`, 93 `frinta`, `fcvtau` and `fcvtas`. 94 + Added support for assembling and disassembling `isb`, `dsb` and `dmb`. 95 + Added support for automatic inversion of compare instructions when using 96 negative immediates. 97 + Added support for using `movn` when generating immediates. 98 + Added explicit flag-setting 'S' instructions, and removed 99 `SetFlags` and `LeaveFlags` arguments. 100 + Added support for `Movk` in macro assembler. 101 + Added support for W register parameters to `Tbz` and `Tbnz`. 102 + Added support for using immediate operands with `Csel`. 103 + Added new debugger syntax for memory inspection. 104 + Fixed `smull`, `fmsub` and `sdiv` simulation. 105 + Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`. 106 + Prevented code generation for certain side-effect free operations, 107 such as `add r, r, #0`, in the macro assembler. 108 + Other small bug fixes. 109 110* 1.1 111 + Improved robustness of instruction decoder and disassembler. 112 + Added support for double-to-float conversions using `fcvt`. 113 + Added support for more fixed-point to floating-point conversions (`ucvtf` 114 and `scvtf`). 115 + Added instruction statistics collection class `instrument-a64.cc`. 116 117* 1.0 118 + Initial release. 119