Lines Matching refs:SRL
1116 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1387 case ISD::SRL: return visitSRL(N); in visit()
1486 case ISD::SRL: in combine()
2281 SDValue SRL = in visitSDIV() local
2282 DAG.getNode(ISD::SRL, DL, VT, SGN, in visitSDIV()
2285 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL); in visitSDIV()
2286 AddToWorklist(SRL.getNode()); in visitSDIV()
2347 return DAG.getNode(ISD::SRL, DL, VT, N0, in visitUDIV()
2362 return DAG.getNode(ISD::SRL, DL, VT, N0, Add); in visitUDIV()
2505 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2541 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
2620 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
2651 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
2752 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || in SimplifyBinOpWithSameOpcodeHands()
2939 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
3331 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
3355 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
3357 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
3417 Res = DAG.getNode(ISD::SRL, DL, VT, Res, in MatchBSwapHWordLow()
3435 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
3458 if (N0.getOpcode() != ISD::SRL) in isBSwapHWordElement()
3571 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt)); in MatchBSwapHWord()
3831 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in MatchRotateHalf()
4282 BinOpLHSVal->getOpcode() != ISD::SRL) || in visitShiftByConstant()
4463 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
4485 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) && in visitSHL()
4503 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitSHL()
4518 Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), in visitSHL()
4655 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, in visitSRA()
4676 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
4705 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); in visitSRA()
4732 return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C); in visitSRL()
4748 if (N1C && N0.getOpcode() == ISD::SRL) { in visitSRL()
4755 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), in visitSRL()
4762 N0.getOperand(0).getOpcode() == ISD::SRL && in visitSRL()
4776 DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
4802 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
4805 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
4822 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); in visitSRL()
4851 Op = DAG.getNode(ISD::SRL, DL, VT, Op, in visitSRL()
4867 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1); in visitSRL()
6493 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
6698 case ISD::SRL: in GetDemandedBits()
6710 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(), in GetDemandedBits()
6739 } else if (Opc == ISD::SRL) { in ReduceLoadWidth()
6759 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in ReduceLoadWidth()
6942 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
7400 X = DAG.getNode(ISD::SRL, DL, in visitBITCAST()
9340 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || in visitBRCOND()
9343 N1.getOperand(0).getOpcode() == ISD::SRL))) { in visitBRCOND()
10531 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
10701 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal, in ShrinkLoadReplaceStoreWithStore()
14085 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), in SimplifySelectCC()