416   SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);  in ExpandUnalignedStore()
828               ISD::SRL, dl, Value.getValueType(), Value,  in LegalizeStoreOps()
840               ISD::SRL, dl, Value.getValueType(), Value,  in LegalizeStoreOps()
1358     case ISD::SRL:  in LegalizeOp()
2602     SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,  in ExpandLegalINT_TO_FP()
2623       SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);  in ExpandLegalINT_TO_FP()
2659     SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,  in ExpandLegalINT_TO_FP()
2825           DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));  in ExpandBITREVERSE()
2845     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));  in ExpandBSWAP()
2850     Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));  in ExpandBSWAP()
2851     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));  in ExpandBSWAP()
2863     Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));  in ExpandBSWAP()
2864     Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));  in ExpandBSWAP()
2865     Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));  in ExpandBSWAP()
2866     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));  in ExpandBSWAP()
2917                                  DAG.getNode(ISD::SRL, dl, VT, Op,  in ExpandBitCount()
2924                                  DAG.getNode(ISD::SRL, dl, VT, Op,  in ExpandBitCount()
2930                                  DAG.getNode(ISD::SRL, dl, VT, Op,  in ExpandBitCount()
2934     Op = DAG.getNode(ISD::SRL, dl, VT,  in ExpandBitCount()
2959                        DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));  in ExpandBitCount()
3294       Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),  in ExpandNode()
3913   case ISD::SRL:  in ExpandNode()
4260         ISD::SRL, dl, NVT, Tmp1,  in PromoteNode()