983                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
993     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
995   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1059                                        unsigned DefIdx) const {  in hasLowDefLatency()
1065   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1073                   const MachineInstr *DefMI, unsigned DefIdx,  in getOperandLatency()  argument
1077   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1110                       const MachineInstr *DefMI, unsigned DefIdx,  in computeOperandLatency()  argument
1121     OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);  in computeOperandLatency()
1124     OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);  in computeOperandLatency()
1139     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1145     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1149   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1164     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1170     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1174   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1187     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1193     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1197   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()