1545     AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);  in copyPhysRegTuple()
1573             .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));  in copyPhysReg()
1576             .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
1597             .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));  in copyPhysReg()
1602             .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1613           .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
1623           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1691           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1695         .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
1716           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1719           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1733           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1736           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1750           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1757           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1771           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1778           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1787         .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1793         .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1800         .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1806         .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
1814       .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
1824       .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));  in copyPhysReg()
1921                                       .addReg(SrcReg, getKillRegState(isKill))  in storeRegToStackSlot()
2642                                 .addReg(SrcReg0, getKillRegState(Src0IsKill))  in genMadd()
2643                                 .addReg(SrcReg1, getKillRegState(Src1IsKill))  in genMadd()
2644                                 .addReg(SrcReg2, getKillRegState(Src2IsKill));  in genMadd()
2690                                 .addReg(SrcReg0, getKillRegState(Src0IsKill))  in genMaddR()
2691                                 .addReg(SrcReg1, getKillRegState(Src1IsKill))  in genMaddR()