Lines Matching refs:ARM
75 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
76 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
77 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
78 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
79 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
80 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
81 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
82 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
85 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
86 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
87 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
88 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
89 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
90 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
91 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
92 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
96 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), in ARMBaseInstrInfo()
180 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
187 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
192 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
203 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
208 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
400 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in InsertBranch()
402 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in InsertBranch()
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { in DefinesPredicate()
521 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
529 case ARM::tADC: // ADC (register) T1 in isEligibleForITBlock()
530 case ARM::tADDi3: // ADD (immediate) T1 in isEligibleForITBlock()
531 case ARM::tADDi8: // ADD (immediate) T2 in isEligibleForITBlock()
532 case ARM::tADDrr: // ADD (register) T1 in isEligibleForITBlock()
533 case ARM::tAND: // AND (register) T1 in isEligibleForITBlock()
534 case ARM::tASRri: // ASR (immediate) T1 in isEligibleForITBlock()
535 case ARM::tASRrr: // ASR (register) T1 in isEligibleForITBlock()
536 case ARM::tBIC: // BIC (register) T1 in isEligibleForITBlock()
537 case ARM::tEOR: // EOR (register) T1 in isEligibleForITBlock()
538 case ARM::tLSLri: // LSL (immediate) T1 in isEligibleForITBlock()
539 case ARM::tLSLrr: // LSL (register) T1 in isEligibleForITBlock()
540 case ARM::tLSRri: // LSR (immediate) T1 in isEligibleForITBlock()
541 case ARM::tLSRrr: // LSR (register) T1 in isEligibleForITBlock()
542 case ARM::tMUL: // MUL T1 in isEligibleForITBlock()
543 case ARM::tMVN: // MVN (register) T1 in isEligibleForITBlock()
544 case ARM::tORR: // ORR (register) T1 in isEligibleForITBlock()
545 case ARM::tROR: // ROR (register) T1 in isEligibleForITBlock()
546 case ARM::tRSB: // RSB (immediate) T1 in isEligibleForITBlock()
547 case ARM::tSBC: // SBC (register) T1 in isEligibleForITBlock()
548 case ARM::tSUBi3: // SUB (immediate) T1 in isEligibleForITBlock()
549 case ARM::tSUBi8: // SUB (immediate) T2 in isEligibleForITBlock()
550 case ARM::tSUBrr: // SUB (register) T1 in isEligibleForITBlock()
585 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
607 if (MI->getOpcode() == ARM::INLINEASM) in GetInstSizeInBytes()
616 case ARM::MOVi16_ga_pcrel: in GetInstSizeInBytes()
617 case ARM::MOVTi16_ga_pcrel: in GetInstSizeInBytes()
618 case ARM::t2MOVi16_ga_pcrel: in GetInstSizeInBytes()
619 case ARM::t2MOVTi16_ga_pcrel: in GetInstSizeInBytes()
621 case ARM::MOVi32imm: in GetInstSizeInBytes()
622 case ARM::t2MOVi32imm: in GetInstSizeInBytes()
624 case ARM::CONSTPOOL_ENTRY: in GetInstSizeInBytes()
625 case ARM::JUMPTABLE_INSTS: in GetInstSizeInBytes()
626 case ARM::JUMPTABLE_ADDRS: in GetInstSizeInBytes()
627 case ARM::JUMPTABLE_TBB: in GetInstSizeInBytes()
628 case ARM::JUMPTABLE_TBH: in GetInstSizeInBytes()
632 case ARM::Int_eh_sjlj_longjmp: in GetInstSizeInBytes()
634 case ARM::tInt_eh_sjlj_longjmp: in GetInstSizeInBytes()
636 case ARM::Int_eh_sjlj_setjmp: in GetInstSizeInBytes()
637 case ARM::Int_eh_sjlj_setjmp_nofp: in GetInstSizeInBytes()
639 case ARM::tInt_eh_sjlj_setjmp: in GetInstSizeInBytes()
640 case ARM::t2Int_eh_sjlj_setjmp: in GetInstSizeInBytes()
641 case ARM::t2Int_eh_sjlj_setjmp_nofp: in GetInstSizeInBytes()
643 case ARM::SPACE: in GetInstSizeInBytes()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
665 : ARM::MRS; in copyFromCPSR()
677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
685 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
686 : ARM::MSR; in copyToCPSR()
699 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
707 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
716 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
720 Opc = ARM::VMOVS; in copyPhysReg()
722 Opc = ARM::VMOVRS; in copyPhysReg()
724 Opc = ARM::VMOVSR; in copyPhysReg()
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
726 Opc = ARM::VMOVD; in copyPhysReg()
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
728 Opc = ARM::VORRq; in copyPhysReg()
733 if (Opc == ARM::VORRq) in copyPhysReg()
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
746 Opc = ARM::VORRq; in copyPhysReg()
747 BeginIdx = ARM::qsub_0; in copyPhysReg()
749 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
750 Opc = ARM::VORRq; in copyPhysReg()
751 BeginIdx = ARM::qsub_0; in copyPhysReg()
754 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
755 Opc = ARM::VMOVD; in copyPhysReg()
756 BeginIdx = ARM::dsub_0; in copyPhysReg()
758 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
759 Opc = ARM::VMOVD; in copyPhysReg()
760 BeginIdx = ARM::dsub_0; in copyPhysReg()
762 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
763 Opc = ARM::VMOVD; in copyPhysReg()
764 BeginIdx = ARM::dsub_0; in copyPhysReg()
766 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
767 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; in copyPhysReg()
768 BeginIdx = ARM::gsub_0; in copyPhysReg()
770 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
771 Opc = ARM::VMOVD; in copyPhysReg()
772 BeginIdx = ARM::dsub_0; in copyPhysReg()
775 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
776 Opc = ARM::VMOVD; in copyPhysReg()
777 BeginIdx = ARM::dsub_0; in copyPhysReg()
780 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
781 Opc = ARM::VMOVD; in copyPhysReg()
782 BeginIdx = ARM::dsub_0; in copyPhysReg()
785 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) { in copyPhysReg()
786 Opc = ARM::VMOVS; in copyPhysReg()
787 BeginIdx = ARM::ssub_0; in copyPhysReg()
789 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
792 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
820 if (Opc == ARM::VORRq) in copyPhysReg()
824 if (Opc == ARM::MOVr) in copyPhysReg()
862 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
863 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) in storeRegToStackSlot()
866 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
867 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) in storeRegToStackSlot()
874 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
875 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) in storeRegToStackSlot()
878 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
880 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot()
881 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
882 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) in storeRegToStackSlot()
892 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
893 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
899 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
902 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) in storeRegToStackSlot()
907 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) in storeRegToStackSlot()
916 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
919 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) in storeRegToStackSlot()
925 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) in storeRegToStackSlot()
928 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
929 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
930 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
936 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
940 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) in storeRegToStackSlot()
946 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) in storeRegToStackSlot()
949 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
950 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
951 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
952 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
958 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
960 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) in storeRegToStackSlot()
963 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
964 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
965 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
966 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
967 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
968 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
969 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
970 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
984 case ARM::STRrs: in isStoreToStackSlot()
985 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. in isStoreToStackSlot()
995 case ARM::STRi12: in isStoreToStackSlot()
996 case ARM::t2STRi12: in isStoreToStackSlot()
997 case ARM::tSTRspi: in isStoreToStackSlot()
998 case ARM::VSTRD: in isStoreToStackSlot()
999 case ARM::VSTRS: in isStoreToStackSlot()
1007 case ARM::VST1q64: in isStoreToStackSlot()
1008 case ARM::VST1d64TPseudo: in isStoreToStackSlot()
1009 case ARM::VST1d64QPseudo: in isStoreToStackSlot()
1016 case ARM::VSTMQIA: in isStoreToStackSlot()
1050 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1051 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1054 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1055 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1061 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1064 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1068 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1069 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1070 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1077 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1079 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1080 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1089 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1091 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1095 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1103 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1105 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1110 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1113 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1114 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1115 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1123 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1125 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1130 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1133 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1134 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1135 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1136 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1144 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1146 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1149 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1150 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1151 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1152 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1156 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1172 case ARM::LDRrs: in isLoadFromStackSlot()
1173 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. in isLoadFromStackSlot()
1183 case ARM::LDRi12: in isLoadFromStackSlot()
1184 case ARM::t2LDRi12: in isLoadFromStackSlot()
1185 case ARM::tLDRspi: in isLoadFromStackSlot()
1186 case ARM::VLDRD: in isLoadFromStackSlot()
1187 case ARM::VLDRS: in isLoadFromStackSlot()
1195 case ARM::VLD1q64: in isLoadFromStackSlot()
1196 case ARM::VLD1d64TPseudo: in isLoadFromStackSlot()
1197 case ARM::VLD1d64QPseudo: in isLoadFromStackSlot()
1204 case ARM::VLDMQIA: in isLoadFromStackSlot()
1235 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1236 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()
1237 : ARM::LDMIA_UPD)) in expandMEMCPY()
1240 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1244 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1245 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
1246 : ARM::STMIA_UPD)) in expandMEMCPY()
1249 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1289 if (MI->getOpcode() == ARM::MEMCPY) { in expandPostRAPseudo()
1306 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) in expandPostRAPseudo()
1310 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1311 &ARM::DPRRegClass); in expandPostRAPseudo()
1312 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1313 &ARM::DPRRegClass); in expandPostRAPseudo()
1338 MI->setDesc(get(ARM::VMOVD)); in expandPostRAPseudo()
1420 case ARM::tLDRpci_pic: in reMaterialize()
1421 case ARM::t2LDRpci_pic: { in reMaterialize()
1438 case ARM::tLDRpci_pic: in duplicate()
1439 case ARM::t2LDRpci_pic: { in duplicate()
1454 if (Opcode == ARM::t2LDRpci || in produceSameValue()
1455 Opcode == ARM::t2LDRpci_pic || in produceSameValue()
1456 Opcode == ARM::tLDRpci || in produceSameValue()
1457 Opcode == ARM::tLDRpci_pic || in produceSameValue()
1458 Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1459 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1460 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1461 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1462 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1463 Opcode == ARM::t2MOV_ga_pcrel) { in produceSameValue()
1474 if (Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1475 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1476 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1477 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1478 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1479 Opcode == ARM::t2MOV_ga_pcrel) in produceSameValue()
1501 } else if (Opcode == ARM::PICLDR) { in produceSameValue()
1557 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1558 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1559 case ARM::LDRD: in areLoadsFromSameBasePtr()
1560 case ARM::LDRH: in areLoadsFromSameBasePtr()
1561 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1562 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1563 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1564 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1565 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1566 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1567 case ARM::t2LDRDi8: in areLoadsFromSameBasePtr()
1568 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1569 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1570 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1571 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1578 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1579 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1580 case ARM::LDRD: in areLoadsFromSameBasePtr()
1581 case ARM::LDRH: in areLoadsFromSameBasePtr()
1582 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1583 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1584 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1585 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1586 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1587 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1588 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1589 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1590 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1591 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1643 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
1644 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
1645 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
1646 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
1682 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
1693 if (!MI->isCall() && MI->definesRegister(ARM::SP)) in isSchedulingBoundary()
1713 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
1717 if (CmpMI->getOpcode() == ARM::tCMPi8 || in isProfitableToIfCvt()
1718 CmpMI->getOpcode() == ARM::t2CMPri) { in isProfitableToIfCvt()
1790 if (Opc == ARM::B) in getMatchingCondBranchOpcode()
1791 return ARM::Bcc; in getMatchingCondBranchOpcode()
1792 if (Opc == ARM::tB) in getMatchingCondBranchOpcode()
1793 return ARM::tBcc; in getMatchingCondBranchOpcode()
1794 if (Opc == ARM::t2B) in getMatchingCondBranchOpcode()
1795 return ARM::t2Bcc; in getMatchingCondBranchOpcode()
1805 case ARM::MOVCCr: in commuteInstructionImpl()
1806 case ARM::t2MOVCCr: { in commuteInstructionImpl()
1811 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
1867 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && in analyzeSelect()
1888 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && in optimizeSelect()
1963 {ARM::ADDSri, ARM::ADDri},
1964 {ARM::ADDSrr, ARM::ADDrr},
1965 {ARM::ADDSrsi, ARM::ADDrsi},
1966 {ARM::ADDSrsr, ARM::ADDrsr},
1968 {ARM::SUBSri, ARM::SUBri},
1969 {ARM::SUBSrr, ARM::SUBrr},
1970 {ARM::SUBSrsi, ARM::SUBrsi},
1971 {ARM::SUBSrsr, ARM::SUBrsr},
1973 {ARM::RSBSri, ARM::RSBri},
1974 {ARM::RSBSrsi, ARM::RSBrsi},
1975 {ARM::RSBSrsr, ARM::RSBrsr},
1977 {ARM::t2ADDSri, ARM::t2ADDri},
1978 {ARM::t2ADDSrr, ARM::t2ADDrr},
1979 {ARM::t2ADDSrs, ARM::t2ADDrs},
1981 {ARM::t2SUBSri, ARM::t2SUBri},
1982 {ARM::t2SUBSrr, ARM::t2SUBrr},
1983 {ARM::t2SUBSrs, ARM::t2SUBrs},
1985 {ARM::t2RSBSri, ARM::t2RSBri},
1986 {ARM::t2RSBSrs, ARM::t2RSBrs},
2002 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2023 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2048 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2049 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2050 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2051 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2052 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2054 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2055 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2072 RD0Reg = ARM::D0; in tryFoldSPUpdateIntoPushPop()
2075 RD0Reg = ARM::R0; in tryFoldSPUpdateIntoPushPop()
2149 if (Opcode == ARM::INLINEASM) in rewriteARMFrameIndex()
2152 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2156 MI.setDesc(TII.get(ARM::MOVr)); in rewriteARMFrameIndex()
2164 MI.setDesc(TII.get(ARM::SUBri)); in rewriteARMFrameIndex()
2289 case ARM::CMPri: in analyzeCompare()
2290 case ARM::t2CMPri: in analyzeCompare()
2296 case ARM::CMPrr: in analyzeCompare()
2297 case ARM::t2CMPrr: in analyzeCompare()
2303 case ARM::TSTri: in analyzeCompare()
2304 case ARM::t2TSTri: in analyzeCompare()
2322 case ARM::ANDri: in isSuitableForMask()
2323 case ARM::t2ANDri: in isSuitableForMask()
2361 if ((CmpI->getOpcode() == ARM::CMPrr || in isRedundantFlagInstr()
2362 CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2363 (OI->getOpcode() == ARM::SUBrr || in isRedundantFlagInstr()
2364 OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2371 if ((CmpI->getOpcode() == ARM::CMPri || in isRedundantFlagInstr()
2372 CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2373 (OI->getOpcode() == ARM::SUBri || in isRedundantFlagInstr()
2374 OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2435 if (CmpInstr->getOpcode() == ARM::CMPri || in optimizeCompareInstr()
2436 CmpInstr->getOpcode() == ARM::t2CMPri) in optimizeCompareInstr()
2449 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
2450 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
2479 case ARM::RSBrr: in optimizeCompareInstr()
2480 case ARM::RSBri: in optimizeCompareInstr()
2481 case ARM::RSCrr: in optimizeCompareInstr()
2482 case ARM::RSCri: in optimizeCompareInstr()
2483 case ARM::ADDrr: in optimizeCompareInstr()
2484 case ARM::ADDri: in optimizeCompareInstr()
2485 case ARM::ADCrr: in optimizeCompareInstr()
2486 case ARM::ADCri: in optimizeCompareInstr()
2487 case ARM::SUBrr: in optimizeCompareInstr()
2488 case ARM::SUBri: in optimizeCompareInstr()
2489 case ARM::SBCrr: in optimizeCompareInstr()
2490 case ARM::SBCri: in optimizeCompareInstr()
2491 case ARM::t2RSBri: in optimizeCompareInstr()
2492 case ARM::t2ADDrr: in optimizeCompareInstr()
2493 case ARM::t2ADDri: in optimizeCompareInstr()
2494 case ARM::t2ADCrr: in optimizeCompareInstr()
2495 case ARM::t2ADCri: in optimizeCompareInstr()
2496 case ARM::t2SUBrr: in optimizeCompareInstr()
2497 case ARM::t2SUBri: in optimizeCompareInstr()
2498 case ARM::t2SBCrr: in optimizeCompareInstr()
2499 case ARM::t2SBCri: in optimizeCompareInstr()
2500 case ARM::ANDrr: in optimizeCompareInstr()
2501 case ARM::ANDri: in optimizeCompareInstr()
2502 case ARM::t2ANDrr: in optimizeCompareInstr()
2503 case ARM::t2ANDri: in optimizeCompareInstr()
2504 case ARM::ORRrr: in optimizeCompareInstr()
2505 case ARM::ORRri: in optimizeCompareInstr()
2506 case ARM::t2ORRrr: in optimizeCompareInstr()
2507 case ARM::t2ORRri: in optimizeCompareInstr()
2508 case ARM::EORrr: in optimizeCompareInstr()
2509 case ARM::EORri: in optimizeCompareInstr()
2510 case ARM::t2EORrr: in optimizeCompareInstr()
2511 case ARM::t2EORri: { in optimizeCompareInstr()
2528 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
2532 if (!MO.isReg() || MO.getReg() != ARM::CPSR) in optimizeCompareInstr()
2546 case ARM::VSELEQD: in optimizeCompareInstr()
2547 case ARM::VSELEQS: in optimizeCompareInstr()
2550 case ARM::VSELGTD: in optimizeCompareInstr()
2551 case ARM::VSELGTS: in optimizeCompareInstr()
2554 case ARM::VSELGED: in optimizeCompareInstr()
2555 case ARM::VSELGES: in optimizeCompareInstr()
2558 case ARM::VSELVSS: in optimizeCompareInstr()
2559 case ARM::VSELVSD: in optimizeCompareInstr()
2614 if ((*SI)->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
2619 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
2641 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) in FoldImmediate()
2654 if (MO.getReg() == ARM::CPSR && !MO.isDead()) in FoldImmediate()
2663 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) in FoldImmediate()
2676 case ARM::SUBrr: in FoldImmediate()
2677 case ARM::ADDrr: in FoldImmediate()
2678 case ARM::ORRrr: in FoldImmediate()
2679 case ARM::EORrr: in FoldImmediate()
2680 case ARM::t2SUBrr: in FoldImmediate()
2681 case ARM::t2ADDrr: in FoldImmediate()
2682 case ARM::t2ORRrr: in FoldImmediate()
2683 case ARM::t2EORrr: { in FoldImmediate()
2687 case ARM::SUBrr: { in FoldImmediate()
2691 NewUseOpc = ARM::SUBri; in FoldImmediate()
2694 case ARM::ADDrr: in FoldImmediate()
2695 case ARM::ORRrr: in FoldImmediate()
2696 case ARM::EORrr: { in FoldImmediate()
2703 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; in FoldImmediate()
2704 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; in FoldImmediate()
2705 case ARM::EORrr: NewUseOpc = ARM::EORri; break; in FoldImmediate()
2709 case ARM::t2SUBrr: { in FoldImmediate()
2713 NewUseOpc = ARM::t2SUBri; in FoldImmediate()
2716 case ARM::t2ADDrr: in FoldImmediate()
2717 case ARM::t2ORRrr: in FoldImmediate()
2718 case ARM::t2EORrr: { in FoldImmediate()
2725 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; in FoldImmediate()
2726 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; in FoldImmediate()
2727 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; in FoldImmediate()
2762 case ARM::LDRrs: in getNumMicroOpsSwiftLdSt()
2763 case ARM::LDRBrs: in getNumMicroOpsSwiftLdSt()
2764 case ARM::STRrs: in getNumMicroOpsSwiftLdSt()
2765 case ARM::STRBrs: { in getNumMicroOpsSwiftLdSt()
2777 case ARM::LDRH: in getNumMicroOpsSwiftLdSt()
2778 case ARM::STRH: { in getNumMicroOpsSwiftLdSt()
2793 case ARM::LDRSB: in getNumMicroOpsSwiftLdSt()
2794 case ARM::LDRSH: in getNumMicroOpsSwiftLdSt()
2797 case ARM::LDRSB_POST: in getNumMicroOpsSwiftLdSt()
2798 case ARM::LDRSH_POST: { in getNumMicroOpsSwiftLdSt()
2804 case ARM::LDR_PRE_REG: in getNumMicroOpsSwiftLdSt()
2805 case ARM::LDRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
2821 case ARM::STR_PRE_REG: in getNumMicroOpsSwiftLdSt()
2822 case ARM::STRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
2834 case ARM::LDRH_PRE: in getNumMicroOpsSwiftLdSt()
2835 case ARM::STRH_PRE: { in getNumMicroOpsSwiftLdSt()
2846 case ARM::LDR_POST_REG: in getNumMicroOpsSwiftLdSt()
2847 case ARM::LDRB_POST_REG: in getNumMicroOpsSwiftLdSt()
2848 case ARM::LDRH_POST: { in getNumMicroOpsSwiftLdSt()
2854 case ARM::LDR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2855 case ARM::LDRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2856 case ARM::LDR_POST_IMM: in getNumMicroOpsSwiftLdSt()
2857 case ARM::LDRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
2858 case ARM::STRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
2859 case ARM::STRB_POST_REG: in getNumMicroOpsSwiftLdSt()
2860 case ARM::STRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2861 case ARM::STRH_POST: in getNumMicroOpsSwiftLdSt()
2862 case ARM::STR_POST_IMM: in getNumMicroOpsSwiftLdSt()
2863 case ARM::STR_POST_REG: in getNumMicroOpsSwiftLdSt()
2864 case ARM::STR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2867 case ARM::LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
2868 case ARM::LDRSH_PRE: { in getNumMicroOpsSwiftLdSt()
2886 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
2895 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
2902 case ARM::LDRD_POST: in getNumMicroOpsSwiftLdSt()
2903 case ARM::t2LDRD_POST: in getNumMicroOpsSwiftLdSt()
2906 case ARM::STRD_POST: in getNumMicroOpsSwiftLdSt()
2907 case ARM::t2STRD_POST: in getNumMicroOpsSwiftLdSt()
2910 case ARM::LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
2919 case ARM::t2LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
2925 case ARM::STRD_PRE: { in getNumMicroOpsSwiftLdSt()
2932 case ARM::t2STRD_PRE: in getNumMicroOpsSwiftLdSt()
2935 case ARM::t2LDR_POST: in getNumMicroOpsSwiftLdSt()
2936 case ARM::t2LDRB_POST: in getNumMicroOpsSwiftLdSt()
2937 case ARM::t2LDRB_PRE: in getNumMicroOpsSwiftLdSt()
2938 case ARM::t2LDRSBi12: in getNumMicroOpsSwiftLdSt()
2939 case ARM::t2LDRSBi8: in getNumMicroOpsSwiftLdSt()
2940 case ARM::t2LDRSBpci: in getNumMicroOpsSwiftLdSt()
2941 case ARM::t2LDRSBs: in getNumMicroOpsSwiftLdSt()
2942 case ARM::t2LDRH_POST: in getNumMicroOpsSwiftLdSt()
2943 case ARM::t2LDRH_PRE: in getNumMicroOpsSwiftLdSt()
2944 case ARM::t2LDRSBT: in getNumMicroOpsSwiftLdSt()
2945 case ARM::t2LDRSB_POST: in getNumMicroOpsSwiftLdSt()
2946 case ARM::t2LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
2947 case ARM::t2LDRSH_POST: in getNumMicroOpsSwiftLdSt()
2948 case ARM::t2LDRSH_PRE: in getNumMicroOpsSwiftLdSt()
2949 case ARM::t2LDRSHi12: in getNumMicroOpsSwiftLdSt()
2950 case ARM::t2LDRSHi8: in getNumMicroOpsSwiftLdSt()
2951 case ARM::t2LDRSHpci: in getNumMicroOpsSwiftLdSt()
2952 case ARM::t2LDRSHs: in getNumMicroOpsSwiftLdSt()
2955 case ARM::t2LDRDi8: { in getNumMicroOpsSwiftLdSt()
2961 case ARM::t2STRB_POST: in getNumMicroOpsSwiftLdSt()
2962 case ARM::t2STRB_PRE: in getNumMicroOpsSwiftLdSt()
2963 case ARM::t2STRBs: in getNumMicroOpsSwiftLdSt()
2964 case ARM::t2STRDi8: in getNumMicroOpsSwiftLdSt()
2965 case ARM::t2STRH_POST: in getNumMicroOpsSwiftLdSt()
2966 case ARM::t2STRH_PRE: in getNumMicroOpsSwiftLdSt()
2967 case ARM::t2STRHs: in getNumMicroOpsSwiftLdSt()
2968 case ARM::t2STR_POST: in getNumMicroOpsSwiftLdSt()
2969 case ARM::t2STR_PRE: in getNumMicroOpsSwiftLdSt()
2970 case ARM::t2STRs: in getNumMicroOpsSwiftLdSt()
3026 case ARM::VLDMQIA: in getNumMicroOps()
3027 case ARM::VSTMQIA: in getNumMicroOps()
3040 case ARM::VLDMDIA: in getNumMicroOps()
3041 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3042 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3043 case ARM::VLDMSIA: in getNumMicroOps()
3044 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3045 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3046 case ARM::VSTMDIA: in getNumMicroOps()
3047 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3048 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3049 case ARM::VSTMSIA: in getNumMicroOps()
3050 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3051 case ARM::VSTMSDB_UPD: { in getNumMicroOps()
3056 case ARM::LDMIA_RET: in getNumMicroOps()
3057 case ARM::LDMIA: in getNumMicroOps()
3058 case ARM::LDMDA: in getNumMicroOps()
3059 case ARM::LDMDB: in getNumMicroOps()
3060 case ARM::LDMIB: in getNumMicroOps()
3061 case ARM::LDMIA_UPD: in getNumMicroOps()
3062 case ARM::LDMDA_UPD: in getNumMicroOps()
3063 case ARM::LDMDB_UPD: in getNumMicroOps()
3064 case ARM::LDMIB_UPD: in getNumMicroOps()
3065 case ARM::STMIA: in getNumMicroOps()
3066 case ARM::STMDA: in getNumMicroOps()
3067 case ARM::STMDB: in getNumMicroOps()
3068 case ARM::STMIB: in getNumMicroOps()
3069 case ARM::STMIA_UPD: in getNumMicroOps()
3070 case ARM::STMDA_UPD: in getNumMicroOps()
3071 case ARM::STMDB_UPD: in getNumMicroOps()
3072 case ARM::STMIB_UPD: in getNumMicroOps()
3073 case ARM::tLDMIA: in getNumMicroOps()
3074 case ARM::tLDMIA_UPD: in getNumMicroOps()
3075 case ARM::tSTMIA_UPD: in getNumMicroOps()
3076 case ARM::tPOP_RET: in getNumMicroOps()
3077 case ARM::tPOP: in getNumMicroOps()
3078 case ARM::tPUSH: in getNumMicroOps()
3079 case ARM::t2LDMIA_RET: in getNumMicroOps()
3080 case ARM::t2LDMIA: in getNumMicroOps()
3081 case ARM::t2LDMDB: in getNumMicroOps()
3082 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3083 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3084 case ARM::t2STMIA: in getNumMicroOps()
3085 case ARM::t2STMDB: in getNumMicroOps()
3086 case ARM::t2STMIA_UPD: in getNumMicroOps()
3087 case ARM::t2STMDB_UPD: { in getNumMicroOps()
3093 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3094 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3095 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3096 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3097 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3098 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3099 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3100 case ARM::VSTMSDB_UPD: in getNumMicroOps()
3101 case ARM::LDMIA_UPD: in getNumMicroOps()
3102 case ARM::LDMDA_UPD: in getNumMicroOps()
3103 case ARM::LDMDB_UPD: in getNumMicroOps()
3104 case ARM::LDMIB_UPD: in getNumMicroOps()
3105 case ARM::STMIA_UPD: in getNumMicroOps()
3106 case ARM::STMDA_UPD: in getNumMicroOps()
3107 case ARM::STMDB_UPD: in getNumMicroOps()
3108 case ARM::STMIB_UPD: in getNumMicroOps()
3109 case ARM::tLDMIA_UPD: in getNumMicroOps()
3110 case ARM::tSTMIA_UPD: in getNumMicroOps()
3111 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3112 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3113 case ARM::t2STMIA_UPD: in getNumMicroOps()
3114 case ARM::t2STMDB_UPD: in getNumMicroOps()
3117 case ARM::LDMIA_RET: in getNumMicroOps()
3118 case ARM::tPOP_RET: in getNumMicroOps()
3119 case ARM::t2LDMIA_RET: in getNumMicroOps()
3172 case ARM::VLDMSIA: in getVLDMDefCycle()
3173 case ARM::VLDMSIA_UPD: in getVLDMDefCycle()
3174 case ARM::VLDMSDB_UPD: in getVLDMDefCycle()
3247 case ARM::VSTMSIA: in getVSTMUseCycle()
3248 case ARM::VSTMSIA_UPD: in getVSTMUseCycle()
3249 case ARM::VSTMSDB_UPD: in getVSTMUseCycle()
3317 case ARM::VLDMDIA: in getOperandLatency()
3318 case ARM::VLDMDIA_UPD: in getOperandLatency()
3319 case ARM::VLDMDDB_UPD: in getOperandLatency()
3320 case ARM::VLDMSIA: in getOperandLatency()
3321 case ARM::VLDMSIA_UPD: in getOperandLatency()
3322 case ARM::VLDMSDB_UPD: in getOperandLatency()
3326 case ARM::LDMIA_RET: in getOperandLatency()
3327 case ARM::LDMIA: in getOperandLatency()
3328 case ARM::LDMDA: in getOperandLatency()
3329 case ARM::LDMDB: in getOperandLatency()
3330 case ARM::LDMIB: in getOperandLatency()
3331 case ARM::LDMIA_UPD: in getOperandLatency()
3332 case ARM::LDMDA_UPD: in getOperandLatency()
3333 case ARM::LDMDB_UPD: in getOperandLatency()
3334 case ARM::LDMIB_UPD: in getOperandLatency()
3335 case ARM::tLDMIA: in getOperandLatency()
3336 case ARM::tLDMIA_UPD: in getOperandLatency()
3337 case ARM::tPUSH: in getOperandLatency()
3338 case ARM::t2LDMIA_RET: in getOperandLatency()
3339 case ARM::t2LDMIA: in getOperandLatency()
3340 case ARM::t2LDMDB: in getOperandLatency()
3341 case ARM::t2LDMIA_UPD: in getOperandLatency()
3342 case ARM::t2LDMDB_UPD: in getOperandLatency()
3358 case ARM::VSTMDIA: in getOperandLatency()
3359 case ARM::VSTMDIA_UPD: in getOperandLatency()
3360 case ARM::VSTMDDB_UPD: in getOperandLatency()
3361 case ARM::VSTMSIA: in getOperandLatency()
3362 case ARM::VSTMSIA_UPD: in getOperandLatency()
3363 case ARM::VSTMSDB_UPD: in getOperandLatency()
3367 case ARM::STMIA: in getOperandLatency()
3368 case ARM::STMDA: in getOperandLatency()
3369 case ARM::STMDB: in getOperandLatency()
3370 case ARM::STMIB: in getOperandLatency()
3371 case ARM::STMIA_UPD: in getOperandLatency()
3372 case ARM::STMDA_UPD: in getOperandLatency()
3373 case ARM::STMDB_UPD: in getOperandLatency()
3374 case ARM::STMIB_UPD: in getOperandLatency()
3375 case ARM::tSTMIA_UPD: in getOperandLatency()
3376 case ARM::tPOP_RET: in getOperandLatency()
3377 case ARM::tPOP: in getOperandLatency()
3378 case ARM::t2STMIA: in getOperandLatency()
3379 case ARM::t2STMDB: in getOperandLatency()
3380 case ARM::t2STMIA_UPD: in getOperandLatency()
3381 case ARM::t2STMDB_UPD: in getOperandLatency()
3445 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
3471 case ARM::LDRrs: in adjustDefLatency()
3472 case ARM::LDRBrs: { in adjustDefLatency()
3480 case ARM::t2LDRs: in adjustDefLatency()
3481 case ARM::t2LDRBs: in adjustDefLatency()
3482 case ARM::t2LDRHs: in adjustDefLatency()
3483 case ARM::t2LDRSHs: { in adjustDefLatency()
3496 case ARM::LDRrs: in adjustDefLatency()
3497 case ARM::LDRBrs: { in adjustDefLatency()
3511 case ARM::t2LDRs: in adjustDefLatency()
3512 case ARM::t2LDRBs: in adjustDefLatency()
3513 case ARM::t2LDRHs: in adjustDefLatency()
3514 case ARM::t2LDRSHs: { in adjustDefLatency()
3527 case ARM::VLD1q8: in adjustDefLatency()
3528 case ARM::VLD1q16: in adjustDefLatency()
3529 case ARM::VLD1q32: in adjustDefLatency()
3530 case ARM::VLD1q64: in adjustDefLatency()
3531 case ARM::VLD1q8wb_fixed: in adjustDefLatency()
3532 case ARM::VLD1q16wb_fixed: in adjustDefLatency()
3533 case ARM::VLD1q32wb_fixed: in adjustDefLatency()
3534 case ARM::VLD1q64wb_fixed: in adjustDefLatency()
3535 case ARM::VLD1q8wb_register: in adjustDefLatency()
3536 case ARM::VLD1q16wb_register: in adjustDefLatency()
3537 case ARM::VLD1q32wb_register: in adjustDefLatency()
3538 case ARM::VLD1q64wb_register: in adjustDefLatency()
3539 case ARM::VLD2d8: in adjustDefLatency()
3540 case ARM::VLD2d16: in adjustDefLatency()
3541 case ARM::VLD2d32: in adjustDefLatency()
3542 case ARM::VLD2q8: in adjustDefLatency()
3543 case ARM::VLD2q16: in adjustDefLatency()
3544 case ARM::VLD2q32: in adjustDefLatency()
3545 case ARM::VLD2d8wb_fixed: in adjustDefLatency()
3546 case ARM::VLD2d16wb_fixed: in adjustDefLatency()
3547 case ARM::VLD2d32wb_fixed: in adjustDefLatency()
3548 case ARM::VLD2q8wb_fixed: in adjustDefLatency()
3549 case ARM::VLD2q16wb_fixed: in adjustDefLatency()
3550 case ARM::VLD2q32wb_fixed: in adjustDefLatency()
3551 case ARM::VLD2d8wb_register: in adjustDefLatency()
3552 case ARM::VLD2d16wb_register: in adjustDefLatency()
3553 case ARM::VLD2d32wb_register: in adjustDefLatency()
3554 case ARM::VLD2q8wb_register: in adjustDefLatency()
3555 case ARM::VLD2q16wb_register: in adjustDefLatency()
3556 case ARM::VLD2q32wb_register: in adjustDefLatency()
3557 case ARM::VLD3d8: in adjustDefLatency()
3558 case ARM::VLD3d16: in adjustDefLatency()
3559 case ARM::VLD3d32: in adjustDefLatency()
3560 case ARM::VLD1d64T: in adjustDefLatency()
3561 case ARM::VLD3d8_UPD: in adjustDefLatency()
3562 case ARM::VLD3d16_UPD: in adjustDefLatency()
3563 case ARM::VLD3d32_UPD: in adjustDefLatency()
3564 case ARM::VLD1d64Twb_fixed: in adjustDefLatency()
3565 case ARM::VLD1d64Twb_register: in adjustDefLatency()
3566 case ARM::VLD3q8_UPD: in adjustDefLatency()
3567 case ARM::VLD3q16_UPD: in adjustDefLatency()
3568 case ARM::VLD3q32_UPD: in adjustDefLatency()
3569 case ARM::VLD4d8: in adjustDefLatency()
3570 case ARM::VLD4d16: in adjustDefLatency()
3571 case ARM::VLD4d32: in adjustDefLatency()
3572 case ARM::VLD1d64Q: in adjustDefLatency()
3573 case ARM::VLD4d8_UPD: in adjustDefLatency()
3574 case ARM::VLD4d16_UPD: in adjustDefLatency()
3575 case ARM::VLD4d32_UPD: in adjustDefLatency()
3576 case ARM::VLD1d64Qwb_fixed: in adjustDefLatency()
3577 case ARM::VLD1d64Qwb_register: in adjustDefLatency()
3578 case ARM::VLD4q8_UPD: in adjustDefLatency()
3579 case ARM::VLD4q16_UPD: in adjustDefLatency()
3580 case ARM::VLD4q32_UPD: in adjustDefLatency()
3581 case ARM::VLD1DUPq8: in adjustDefLatency()
3582 case ARM::VLD1DUPq16: in adjustDefLatency()
3583 case ARM::VLD1DUPq32: in adjustDefLatency()
3584 case ARM::VLD1DUPq8wb_fixed: in adjustDefLatency()
3585 case ARM::VLD1DUPq16wb_fixed: in adjustDefLatency()
3586 case ARM::VLD1DUPq32wb_fixed: in adjustDefLatency()
3587 case ARM::VLD1DUPq8wb_register: in adjustDefLatency()
3588 case ARM::VLD1DUPq16wb_register: in adjustDefLatency()
3589 case ARM::VLD1DUPq32wb_register: in adjustDefLatency()
3590 case ARM::VLD2DUPd8: in adjustDefLatency()
3591 case ARM::VLD2DUPd16: in adjustDefLatency()
3592 case ARM::VLD2DUPd32: in adjustDefLatency()
3593 case ARM::VLD2DUPd8wb_fixed: in adjustDefLatency()
3594 case ARM::VLD2DUPd16wb_fixed: in adjustDefLatency()
3595 case ARM::VLD2DUPd32wb_fixed: in adjustDefLatency()
3596 case ARM::VLD2DUPd8wb_register: in adjustDefLatency()
3597 case ARM::VLD2DUPd16wb_register: in adjustDefLatency()
3598 case ARM::VLD2DUPd32wb_register: in adjustDefLatency()
3599 case ARM::VLD4DUPd8: in adjustDefLatency()
3600 case ARM::VLD4DUPd16: in adjustDefLatency()
3601 case ARM::VLD4DUPd32: in adjustDefLatency()
3602 case ARM::VLD4DUPd8_UPD: in adjustDefLatency()
3603 case ARM::VLD4DUPd16_UPD: in adjustDefLatency()
3604 case ARM::VLD4DUPd32_UPD: in adjustDefLatency()
3605 case ARM::VLD1LNd8: in adjustDefLatency()
3606 case ARM::VLD1LNd16: in adjustDefLatency()
3607 case ARM::VLD1LNd32: in adjustDefLatency()
3608 case ARM::VLD1LNd8_UPD: in adjustDefLatency()
3609 case ARM::VLD1LNd16_UPD: in adjustDefLatency()
3610 case ARM::VLD1LNd32_UPD: in adjustDefLatency()
3611 case ARM::VLD2LNd8: in adjustDefLatency()
3612 case ARM::VLD2LNd16: in adjustDefLatency()
3613 case ARM::VLD2LNd32: in adjustDefLatency()
3614 case ARM::VLD2LNq16: in adjustDefLatency()
3615 case ARM::VLD2LNq32: in adjustDefLatency()
3616 case ARM::VLD2LNd8_UPD: in adjustDefLatency()
3617 case ARM::VLD2LNd16_UPD: in adjustDefLatency()
3618 case ARM::VLD2LNd32_UPD: in adjustDefLatency()
3619 case ARM::VLD2LNq16_UPD: in adjustDefLatency()
3620 case ARM::VLD2LNq32_UPD: in adjustDefLatency()
3621 case ARM::VLD4LNd8: in adjustDefLatency()
3622 case ARM::VLD4LNd16: in adjustDefLatency()
3623 case ARM::VLD4LNd32: in adjustDefLatency()
3624 case ARM::VLD4LNq16: in adjustDefLatency()
3625 case ARM::VLD4LNq32: in adjustDefLatency()
3626 case ARM::VLD4LNd8_UPD: in adjustDefLatency()
3627 case ARM::VLD4LNd16_UPD: in adjustDefLatency()
3628 case ARM::VLD4LNd32_UPD: in adjustDefLatency()
3629 case ARM::VLD4LNq16_UPD: in adjustDefLatency()
3630 case ARM::VLD4LNq32_UPD: in adjustDefLatency()
3679 if (Reg == ARM::CPSR) { in getOperandLatency()
3680 if (DefMI->getOpcode() == ARM::FMSTAT) { in getOperandLatency()
3772 case ARM::LDRrs: in getOperandLatency()
3773 case ARM::LDRBrs: { in getOperandLatency()
3782 case ARM::t2LDRs: in getOperandLatency()
3783 case ARM::t2LDRBs: in getOperandLatency()
3784 case ARM::t2LDRHs: in getOperandLatency()
3785 case ARM::t2LDRSHs: { in getOperandLatency()
3799 case ARM::LDRrs: in getOperandLatency()
3800 case ARM::LDRBrs: { in getOperandLatency()
3812 case ARM::t2LDRs: in getOperandLatency()
3813 case ARM::t2LDRBs: in getOperandLatency()
3814 case ARM::t2LDRHs: in getOperandLatency()
3815 case ARM::t2LDRSHs: { in getOperandLatency()
3826 case ARM::VLD1q8: in getOperandLatency()
3827 case ARM::VLD1q16: in getOperandLatency()
3828 case ARM::VLD1q32: in getOperandLatency()
3829 case ARM::VLD1q64: in getOperandLatency()
3830 case ARM::VLD1q8wb_register: in getOperandLatency()
3831 case ARM::VLD1q16wb_register: in getOperandLatency()
3832 case ARM::VLD1q32wb_register: in getOperandLatency()
3833 case ARM::VLD1q64wb_register: in getOperandLatency()
3834 case ARM::VLD1q8wb_fixed: in getOperandLatency()
3835 case ARM::VLD1q16wb_fixed: in getOperandLatency()
3836 case ARM::VLD1q32wb_fixed: in getOperandLatency()
3837 case ARM::VLD1q64wb_fixed: in getOperandLatency()
3838 case ARM::VLD2d8: in getOperandLatency()
3839 case ARM::VLD2d16: in getOperandLatency()
3840 case ARM::VLD2d32: in getOperandLatency()
3841 case ARM::VLD2q8Pseudo: in getOperandLatency()
3842 case ARM::VLD2q16Pseudo: in getOperandLatency()
3843 case ARM::VLD2q32Pseudo: in getOperandLatency()
3844 case ARM::VLD2d8wb_fixed: in getOperandLatency()
3845 case ARM::VLD2d16wb_fixed: in getOperandLatency()
3846 case ARM::VLD2d32wb_fixed: in getOperandLatency()
3847 case ARM::VLD2q8PseudoWB_fixed: in getOperandLatency()
3848 case ARM::VLD2q16PseudoWB_fixed: in getOperandLatency()
3849 case ARM::VLD2q32PseudoWB_fixed: in getOperandLatency()
3850 case ARM::VLD2d8wb_register: in getOperandLatency()
3851 case ARM::VLD2d16wb_register: in getOperandLatency()
3852 case ARM::VLD2d32wb_register: in getOperandLatency()
3853 case ARM::VLD2q8PseudoWB_register: in getOperandLatency()
3854 case ARM::VLD2q16PseudoWB_register: in getOperandLatency()
3855 case ARM::VLD2q32PseudoWB_register: in getOperandLatency()
3856 case ARM::VLD3d8Pseudo: in getOperandLatency()
3857 case ARM::VLD3d16Pseudo: in getOperandLatency()
3858 case ARM::VLD3d32Pseudo: in getOperandLatency()
3859 case ARM::VLD1d64TPseudo: in getOperandLatency()
3860 case ARM::VLD1d64TPseudoWB_fixed: in getOperandLatency()
3861 case ARM::VLD3d8Pseudo_UPD: in getOperandLatency()
3862 case ARM::VLD3d16Pseudo_UPD: in getOperandLatency()
3863 case ARM::VLD3d32Pseudo_UPD: in getOperandLatency()
3864 case ARM::VLD3q8Pseudo_UPD: in getOperandLatency()
3865 case ARM::VLD3q16Pseudo_UPD: in getOperandLatency()
3866 case ARM::VLD3q32Pseudo_UPD: in getOperandLatency()
3867 case ARM::VLD3q8oddPseudo: in getOperandLatency()
3868 case ARM::VLD3q16oddPseudo: in getOperandLatency()
3869 case ARM::VLD3q32oddPseudo: in getOperandLatency()
3870 case ARM::VLD3q8oddPseudo_UPD: in getOperandLatency()
3871 case ARM::VLD3q16oddPseudo_UPD: in getOperandLatency()
3872 case ARM::VLD3q32oddPseudo_UPD: in getOperandLatency()
3873 case ARM::VLD4d8Pseudo: in getOperandLatency()
3874 case ARM::VLD4d16Pseudo: in getOperandLatency()
3875 case ARM::VLD4d32Pseudo: in getOperandLatency()
3876 case ARM::VLD1d64QPseudo: in getOperandLatency()
3877 case ARM::VLD1d64QPseudoWB_fixed: in getOperandLatency()
3878 case ARM::VLD4d8Pseudo_UPD: in getOperandLatency()
3879 case ARM::VLD4d16Pseudo_UPD: in getOperandLatency()
3880 case ARM::VLD4d32Pseudo_UPD: in getOperandLatency()
3881 case ARM::VLD4q8Pseudo_UPD: in getOperandLatency()
3882 case ARM::VLD4q16Pseudo_UPD: in getOperandLatency()
3883 case ARM::VLD4q32Pseudo_UPD: in getOperandLatency()
3884 case ARM::VLD4q8oddPseudo: in getOperandLatency()
3885 case ARM::VLD4q16oddPseudo: in getOperandLatency()
3886 case ARM::VLD4q32oddPseudo: in getOperandLatency()
3887 case ARM::VLD4q8oddPseudo_UPD: in getOperandLatency()
3888 case ARM::VLD4q16oddPseudo_UPD: in getOperandLatency()
3889 case ARM::VLD4q32oddPseudo_UPD: in getOperandLatency()
3890 case ARM::VLD1DUPq8: in getOperandLatency()
3891 case ARM::VLD1DUPq16: in getOperandLatency()
3892 case ARM::VLD1DUPq32: in getOperandLatency()
3893 case ARM::VLD1DUPq8wb_fixed: in getOperandLatency()
3894 case ARM::VLD1DUPq16wb_fixed: in getOperandLatency()
3895 case ARM::VLD1DUPq32wb_fixed: in getOperandLatency()
3896 case ARM::VLD1DUPq8wb_register: in getOperandLatency()
3897 case ARM::VLD1DUPq16wb_register: in getOperandLatency()
3898 case ARM::VLD1DUPq32wb_register: in getOperandLatency()
3899 case ARM::VLD2DUPd8: in getOperandLatency()
3900 case ARM::VLD2DUPd16: in getOperandLatency()
3901 case ARM::VLD2DUPd32: in getOperandLatency()
3902 case ARM::VLD2DUPd8wb_fixed: in getOperandLatency()
3903 case ARM::VLD2DUPd16wb_fixed: in getOperandLatency()
3904 case ARM::VLD2DUPd32wb_fixed: in getOperandLatency()
3905 case ARM::VLD2DUPd8wb_register: in getOperandLatency()
3906 case ARM::VLD2DUPd16wb_register: in getOperandLatency()
3907 case ARM::VLD2DUPd32wb_register: in getOperandLatency()
3908 case ARM::VLD4DUPd8Pseudo: in getOperandLatency()
3909 case ARM::VLD4DUPd16Pseudo: in getOperandLatency()
3910 case ARM::VLD4DUPd32Pseudo: in getOperandLatency()
3911 case ARM::VLD4DUPd8Pseudo_UPD: in getOperandLatency()
3912 case ARM::VLD4DUPd16Pseudo_UPD: in getOperandLatency()
3913 case ARM::VLD4DUPd32Pseudo_UPD: in getOperandLatency()
3914 case ARM::VLD1LNq8Pseudo: in getOperandLatency()
3915 case ARM::VLD1LNq16Pseudo: in getOperandLatency()
3916 case ARM::VLD1LNq32Pseudo: in getOperandLatency()
3917 case ARM::VLD1LNq8Pseudo_UPD: in getOperandLatency()
3918 case ARM::VLD1LNq16Pseudo_UPD: in getOperandLatency()
3919 case ARM::VLD1LNq32Pseudo_UPD: in getOperandLatency()
3920 case ARM::VLD2LNd8Pseudo: in getOperandLatency()
3921 case ARM::VLD2LNd16Pseudo: in getOperandLatency()
3922 case ARM::VLD2LNd32Pseudo: in getOperandLatency()
3923 case ARM::VLD2LNq16Pseudo: in getOperandLatency()
3924 case ARM::VLD2LNq32Pseudo: in getOperandLatency()
3925 case ARM::VLD2LNd8Pseudo_UPD: in getOperandLatency()
3926 case ARM::VLD2LNd16Pseudo_UPD: in getOperandLatency()
3927 case ARM::VLD2LNd32Pseudo_UPD: in getOperandLatency()
3928 case ARM::VLD2LNq16Pseudo_UPD: in getOperandLatency()
3929 case ARM::VLD2LNq32Pseudo_UPD: in getOperandLatency()
3930 case ARM::VLD4LNd8Pseudo: in getOperandLatency()
3931 case ARM::VLD4LNd16Pseudo: in getOperandLatency()
3932 case ARM::VLD4LNd32Pseudo: in getOperandLatency()
3933 case ARM::VLD4LNq16Pseudo: in getOperandLatency()
3934 case ARM::VLD4LNq32Pseudo: in getOperandLatency()
3935 case ARM::VLD4LNd8Pseudo_UPD: in getOperandLatency()
3936 case ARM::VLD4LNd16Pseudo_UPD: in getOperandLatency()
3937 case ARM::VLD4LNd32Pseudo_UPD: in getOperandLatency()
3938 case ARM::VLD4LNq16Pseudo_UPD: in getOperandLatency()
3939 case ARM::VLD4LNq32Pseudo_UPD: in getOperandLatency()
3959 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) { in getPredicationCost()
3981 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
3988 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { in getInstrLatency()
4029 case ARM::VLDMQIA: in getInstrLatency()
4030 case ARM::VSTMQIA: in getInstrLatency()
4155 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4161 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4162 MI->getOpcode() == ARM::VMOVS)) in getExecutionDomain()
4184 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4187 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4191 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4225 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
4250 case ARM::VMOVD: in setExecutionDomain()
4268 MI->setDesc(get(ARM::VORRd)); in setExecutionDomain()
4273 case ARM::VMOVRS: in setExecutionDomain()
4290 MI->setDesc(get(ARM::VGETLNi32)); in setExecutionDomain()
4299 case ARM::VMOVSR: { in setExecutionDomain()
4319 MI->setDesc(get(ARM::VSETLNi32)); in setExecutionDomain()
4333 case ARM::VMOVS: { in setExecutionDomain()
4355 MI->setDesc(get(ARM::VDUPLN32d)); in setExecutionDomain()
4384 get(ARM::VEXTd32), DDst); in setExecutionDomain()
4403 MI->setDesc(get(ARM::VEXTd32)); in setExecutionDomain()
4467 case ARM::VLDRS: in getPartialRegUpdateClearance()
4468 case ARM::FCONSTS: in getPartialRegUpdateClearance()
4469 case ARM::VMOVSR: in getPartialRegUpdateClearance()
4470 case ARM::VMOVv8i8: in getPartialRegUpdateClearance()
4471 case ARM::VMOVv4i16: in getPartialRegUpdateClearance()
4472 case ARM::VMOVv2i32: in getPartialRegUpdateClearance()
4473 case ARM::VMOVv2f32: in getPartialRegUpdateClearance()
4474 case ARM::VMOVv1i64: in getPartialRegUpdateClearance()
4479 case ARM::VLD1LNd32: in getPartialRegUpdateClearance()
4496 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
4498 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
4499 &ARM::DPRRegClass); in getPartialRegUpdateClearance()
4525 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
4526 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
4530 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
4542 get(ARM::FCONSTD), DReg).addImm(96)); in breakPartialRegDependency()
4547 return Subtarget.getFeatureBits()[ARM::HasV6KOps]; in hasNOP()
4571 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
4579 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
4583 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
4596 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
4604 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
4617 case ARM::VSETLNi32: in getInsertSubregLikeInputs()
4627 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1; in getInsertSubregLikeInputs()