3154                                   unsigned DefIdx, unsigned DefAlign) const {  in getVLDMDefCycle()  argument
3155   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;  in getVLDMDefCycle()
3158     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3195                                  unsigned DefIdx, unsigned DefAlign) const {  in getLDMDefCycle()  argument
3196   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;  in getLDMDefCycle()
3199     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
3298                                     unsigned DefIdx, unsigned DefAlign,  in getOperandLatency()  argument
3304   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())  in getOperandLatency()
3305     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
3314     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
3323     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
3344     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
3398     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
3409                                            unsigned &DefIdx, unsigned &Dist) {  in getBundledDefMI()  argument
3426   DefIdx = Idx;  in getBundledDefMI()
3644                                     const MachineInstr *DefMI, unsigned DefIdx,  in getOperandLatency()  argument
3651   const MachineOperand &DefMO = DefMI->getOperand(DefIdx);  in getOperandLatency()
3658     DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);  in getOperandLatency()
3714   int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,  in getOperandLatency()
3734                                     SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
3748     int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
3762   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,  in getOperandLatency()
3794   } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {  in getOperandLatency()
4038                       const MachineInstr *DefMI, unsigned DefIdx,  in hasHighOperandLatency()  argument
4049     = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx);  in hasHighOperandLatency()
4058                  const MachineInstr *DefMI, unsigned DefIdx) const {  in hasLowDefLatency()
4066     int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
4565     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceLikeInputs()  argument
4567   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getRegSequenceLikeInputs()
4590     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregLikeInputs()  argument
4592   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getExtractSubregLikeInputs()
4604     InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;  in getExtractSubregLikeInputs()
4611     const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,  in getInsertSubregLikeInputs()  argument
4613   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getInsertSubregLikeInputs()