Lines Matching refs:ARM
113 if ((MI->getOpcode() == ARM::LDR_POST_IMM || in isCSRestore()
114 MI->getOpcode() == ARM::LDR_POST_REG || in isCSRestore()
115 MI->getOpcode() == ARM::t2LDR_POST) && in isCSRestore()
117 MI->getOperand(1).getReg() == ARM::SP) in isCSRestore()
144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
151 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
154 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
155 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
158 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
159 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
258 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
263 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
272 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
276 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
284 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
353 case ARM::R8: in emitPrologue()
354 case ARM::R9: in emitPrologue()
355 case ARM::R10: in emitPrologue()
356 case ARM::R11: in emitPrologue()
357 case ARM::R12: in emitPrologue()
363 case ARM::R0: in emitPrologue()
364 case ARM::R1: in emitPrologue()
365 case ARM::R2: in emitPrologue()
366 case ARM::R3: in emitPrologue()
367 case ARM::R4: in emitPrologue()
368 case ARM::R5: in emitPrologue()
369 case ARM::R6: in emitPrologue()
370 case ARM::R7: in emitPrologue()
371 case ARM::LR: in emitPrologue()
378 if (Reg == ARM::D8) in emitPrologue()
380 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
432 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) { in emitPrologue()
453 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
457 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
466 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
469 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
474 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
478 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
480 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
481 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
486 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), in emitPrologue()
487 ARM::SP) in emitPrologue()
488 .addReg(ARM::SP, RegState::Define) in emitPrologue()
489 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
527 dl, TII, FramePtr, ARM::SP, in emitPrologue()
557 case ARM::R8: in emitPrologue()
558 case ARM::R9: in emitPrologue()
559 case ARM::R10: in emitPrologue()
560 case ARM::R11: in emitPrologue()
561 case ARM::R12: in emitPrologue()
565 case ARM::R0: in emitPrologue()
566 case ARM::R1: in emitPrologue()
567 case ARM::R2: in emitPrologue()
568 case ARM::R3: in emitPrologue()
569 case ARM::R4: in emitPrologue()
570 case ARM::R5: in emitPrologue()
571 case ARM::R6: in emitPrologue()
572 case ARM::R7: in emitPrologue()
573 case ARM::LR: in emitPrologue()
590 case ARM::R8: in emitPrologue()
591 case ARM::R9: in emitPrologue()
592 case ARM::R10: in emitPrologue()
593 case ARM::R11: in emitPrologue()
594 case ARM::R12: in emitPrologue()
616 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && in emitPrologue()
617 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { in emitPrologue()
652 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
662 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
663 .addReg(ARM::SP, RegState::Kill)); in emitPrologue()
664 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
666 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
667 .addReg(ARM::R4, RegState::Kill)); in emitPrologue()
681 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
682 .addReg(ARM::SP) in emitPrologue()
685 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitPrologue()
687 .addReg(ARM::SP)); in emitPrologue()
748 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, in emitEpilogue()
758 assert(!MFI->getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
760 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
762 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitEpilogue()
763 ARM::SP) in emitEpilogue()
764 .addReg(ARM::R4)); in emitEpilogue()
769 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
772 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitEpilogue()
773 ARM::SP) in emitEpilogue()
785 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) in emitEpilogue()
824 FrameReg = ARM::SP; in ResolveFrameIndexReference()
910 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPushInst()
918 if (Reg == ARM::LR) { in emitPushInst()
940 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
941 .addReg(ARM::SP).setMIFlags(MIFlags)); in emitPushInst()
946 ARM::SP) in emitPushInst()
948 .addReg(ARM::SP).setMIFlags(MIFlags) in emitPushInst()
979 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri); in emitPopInst()
981 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; in emitPopInst()
983 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || in emitPopInst()
984 RetOpcode == ARM::tTRAP; in emitPopInst()
997 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPopInst()
1000 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
1003 Reg = ARM::PC; in emitPopInst()
1005 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; in emitPopInst()
1007 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; in emitPopInst()
1025 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1026 .addReg(ARM::SP)); in emitPopInst()
1037 if (Regs[0] == ARM::PC) in emitPopInst()
1038 Regs[0] = ARM::LR; in emitPopInst()
1041 .addReg(ARM::SP, RegState::Define) in emitPopInst()
1042 .addReg(ARM::SP); in emitPopInst()
1045 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { in emitPopInst()
1079 unsigned DNum = CSI[i].getReg() - ARM::D8; in emitAlignedDPRCS2Spills()
1110 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; in emitAlignedDPRCS2Spills()
1111 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1112 .addReg(ARM::SP) in emitAlignedDPRCS2Spills()
1121 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1127 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; in emitAlignedDPRCS2Spills()
1128 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1129 .addReg(ARM::R4); in emitAlignedDPRCS2Spills()
1136 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills()
1141 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1142 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1144 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), in emitAlignedDPRCS2Spills()
1145 ARM::R4) in emitAlignedDPRCS2Spills()
1146 .addReg(ARM::R4, RegState::Kill).addImm(16) in emitAlignedDPRCS2Spills()
1159 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1160 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1162 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1163 .addReg(ARM::R4).addImm(16).addReg(NextReg) in emitAlignedDPRCS2Spills()
1171 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1172 &ARM::QPRRegClass); in emitAlignedDPRCS2Spills()
1174 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1175 .addReg(ARM::R4).addImm(16).addReg(SupReg)); in emitAlignedDPRCS2Spills()
1184 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1186 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2)); in emitAlignedDPRCS2Spills()
1190 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Spills()
1215 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); in skipAlignedDPRCS2Spills()
1237 if (CSI[i].getReg() == ARM::D8) { in emitAlignedDPRCS2Restores()
1250 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in emitAlignedDPRCS2Restores()
1251 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1255 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Restores()
1259 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1260 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1261 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1262 .addReg(ARM::R4, RegState::Define) in emitAlignedDPRCS2Restores()
1263 .addReg(ARM::R4, RegState::Kill).addImm(16) in emitAlignedDPRCS2Restores()
1275 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1276 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1277 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1278 .addReg(ARM::R4).addImm(16) in emitAlignedDPRCS2Restores()
1286 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1287 &ARM::QPRRegClass); in emitAlignedDPRCS2Restores()
1288 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1289 .addReg(ARM::R4).addImm(16)); in emitAlignedDPRCS2Restores()
1296 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1297 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg))); in emitAlignedDPRCS2Restores()
1300 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Restores()
1313 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; in spillCalleeSavedRegisters()
1315 ARM::t2STR_PRE : ARM::STR_PRE_IMM; in spillCalleeSavedRegisters()
1316 unsigned FltOpc = ARM::VSTMDDB_UPD; in spillCalleeSavedRegisters()
1351 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; in restoreCalleeSavedRegisters()
1352 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; in restoreCalleeSavedRegisters()
1353 unsigned FltOpc = ARM::VLDMDIA_UPD; in restoreCalleeSavedRegisters()
1391 if (MI.getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
1462 if (!SavedRegs.test(ARM::D8 + NumSpills)) in checkNumAlignedDPRCS2Regs()
1473 SavedRegs.set(ARM::R4); in checkNumAlignedDPRCS2Regs()
1506 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1511 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1521 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1542 if (!ARM::GPRRegClass.contains(Reg)) in determineCalleeSaves()
1549 if (Reg == ARM::LR) in determineCalleeSaves()
1557 case ARM::LR: in determineCalleeSaves()
1560 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1561 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1562 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1563 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1576 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1577 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1578 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1579 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1580 case ARM::LR: in determineCalleeSaves()
1629 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1633 (unsigned)ARM::LR); in determineCalleeSaves()
1661 (STI.isTargetWindows() && Reg == ARM::R11) || in determineCalleeSaves()
1662 isARMLowRegister(Reg) || Reg == ARM::LR) { in determineCalleeSaves()
1692 Reg == ARM::LR)) { in determineCalleeSaves()
1715 const TargetRegisterClass *RC = &ARM::GPRRegClass; in determineCalleeSaves()
1724 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1758 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
1766 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
1863 unsigned ScratchReg0 = ARM::R4; in adjustForSegmentedStacks()
1864 unsigned ScratchReg1 = ARM::R5; in adjustForSegmentedStacks()
1931 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))) in adjustForSegmentedStacks()
1934 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
1935 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP)) in adjustForSegmentedStacks()
1956 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
1957 .addReg(ARM::SP)); in adjustForSegmentedStacks()
1959 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
1960 .addReg(ARM::SP)).addReg(0); in adjustForSegmentedStacks()
1966 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)) in adjustForSegmentedStacks()
1969 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
1970 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0); in adjustForSegmentedStacks()
1981 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
1985 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
1990 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0) in adjustForSegmentedStacks()
2003 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0) in adjustForSegmentedStacks()
2009 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; in adjustForSegmentedStacks()
2015 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; in adjustForSegmentedStacks()
2018 .addReg(ARM::CPSR); in adjustForSegmentedStacks()
2028 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), in adjustForSegmentedStacks()
2031 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
2038 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)) in adjustForSegmentedStacks()
2041 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
2048 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))) in adjustForSegmentedStacks()
2049 .addReg(ARM::LR); in adjustForSegmentedStacks()
2051 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2052 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2053 .addReg(ARM::SP)) in adjustForSegmentedStacks()
2054 .addReg(ARM::LR); in adjustForSegmentedStacks()
2064 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); in adjustForSegmentedStacks()
2070 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL))) in adjustForSegmentedStacks()
2073 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
2080 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) in adjustForSegmentedStacks()
2082 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
2085 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
2086 .addReg(ARM::LR, RegState::Define) in adjustForSegmentedStacks()
2087 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2088 .addReg(ARM::SP) in adjustForSegmentedStacks()
2092 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2093 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2094 .addReg(ARM::SP)) in adjustForSegmentedStacks()
2095 .addReg(ARM::LR); in adjustForSegmentedStacks()
2103 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) in adjustForSegmentedStacks()
2107 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2108 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2109 .addReg(ARM::SP)) in adjustForSegmentedStacks()
2120 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET; in adjustForSegmentedStacks()
2126 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))) in adjustForSegmentedStacks()
2130 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2131 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2132 .addReg(ARM::SP)) in adjustForSegmentedStacks()