Lines Matching refs:ARM
72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
127 FPReg = ARM::SP; in reset()
249 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
252 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
255 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
258 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
261 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
264 return getSTI().getFeatureBits()[ARM::HasV6MOps]; in hasV6MOps()
267 return getSTI().getFeatureBits()[ARM::HasV7Ops]; in hasV7Ops()
270 return getSTI().getFeatureBits()[ARM::HasV8Ops]; in hasV8Ops()
273 return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; in hasARM()
276 return getSTI().getFeatureBits()[ARM::FeatureDSP]; in hasDSP()
279 return getSTI().getFeatureBits()[ARM::FeatureD16]; in hasD16()
282 return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; in hasV8_1aOps()
287 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); in SwitchMode()
291 return getSTI().getFeatureBits()[ARM::FeatureMClass]; in isMClass()
696 if(Memory.BaseRegNum != ARM::PC) return false; in isThumbMemPC()
1055 if (Memory.BaseRegNum != ARM::PC) in isMemPCRelImm12()
1253 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) in isMemThumbSPI()
1286 if (Memory.BaseRegNum == ARM::PC) return false; in isMemImm8Offset()
1304 if (Memory.BaseRegNum == ARM::PC) return false; in isMemNegImm8Offset()
1366 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPair()
1383 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] in isVecListDPairSpaced()
1410 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPairAllLanes()
1686 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2410 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONinvByteReplicateOperands()
2411 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONinvByteReplicateOperands()
2437 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONvmovByteReplicateOperands()
2438 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONvmovByteReplicateOperands()
2612 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) in CreateRegList()
2614 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. in CreateRegList()
2923 .Case("r13", ARM::SP) in tryParseRegister()
2924 .Case("r14", ARM::LR) in tryParseRegister()
2925 .Case("r15", ARM::PC) in tryParseRegister()
2926 .Case("ip", ARM::R12) in tryParseRegister()
2928 .Case("a1", ARM::R0) in tryParseRegister()
2929 .Case("a2", ARM::R1) in tryParseRegister()
2930 .Case("a3", ARM::R2) in tryParseRegister()
2931 .Case("a4", ARM::R3) in tryParseRegister()
2932 .Case("v1", ARM::R4) in tryParseRegister()
2933 .Case("v2", ARM::R5) in tryParseRegister()
2934 .Case("v3", ARM::R6) in tryParseRegister()
2935 .Case("v4", ARM::R7) in tryParseRegister()
2936 .Case("v5", ARM::R8) in tryParseRegister()
2937 .Case("v6", ARM::R9) in tryParseRegister()
2938 .Case("v7", ARM::R10) in tryParseRegister()
2939 .Case("v8", ARM::R11) in tryParseRegister()
2940 .Case("sb", ARM::R9) in tryParseRegister()
2941 .Case("sl", ARM::R10) in tryParseRegister()
2942 .Case("fp", ARM::R11) in tryParseRegister()
2958 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) in tryParseRegister()
3290 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in getNextRegister()
3294 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
3295 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
3296 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
3297 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
3298 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
3299 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
3300 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
3301 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
3309 case ARM::Q0: return ARM::D0; in getDRegFromQReg()
3310 case ARM::Q1: return ARM::D2; in getDRegFromQReg()
3311 case ARM::Q2: return ARM::D4; in getDRegFromQReg()
3312 case ARM::Q3: return ARM::D6; in getDRegFromQReg()
3313 case ARM::Q4: return ARM::D8; in getDRegFromQReg()
3314 case ARM::Q5: return ARM::D10; in getDRegFromQReg()
3315 case ARM::Q6: return ARM::D12; in getDRegFromQReg()
3316 case ARM::Q7: return ARM::D14; in getDRegFromQReg()
3317 case ARM::Q8: return ARM::D16; in getDRegFromQReg()
3318 case ARM::Q9: return ARM::D18; in getDRegFromQReg()
3319 case ARM::Q10: return ARM::D20; in getDRegFromQReg()
3320 case ARM::Q11: return ARM::D22; in getDRegFromQReg()
3321 case ARM::Q12: return ARM::D24; in getDRegFromQReg()
3322 case ARM::Q13: return ARM::D26; in getDRegFromQReg()
3323 case ARM::Q14: return ARM::D28; in getDRegFromQReg()
3324 case ARM::Q15: return ARM::D30; in getDRegFromQReg()
3349 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
3356 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
3357 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; in parseRegisterList()
3358 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) in parseRegisterList()
3359 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; in parseRegisterList()
3360 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) in parseRegisterList()
3361 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; in parseRegisterList()
3381 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseRegisterList()
3411 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
3420 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
3431 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && in parseRegisterList()
3526 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { in parseVectorList()
3546 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
3553 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
3554 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
3558 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
3559 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
3591 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
3621 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseVectorList()
3628 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { in parseVectorList()
3667 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
3732 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
3733 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
3734 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3745 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
3746 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
3747 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4638 case ARM::tB: in cvtThumbBranches()
4639 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
4641 case ARM::t2B: in cvtThumbBranches()
4642 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
4652 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
4653 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
4660 case ARM::tB: in cvtThumbBranches()
4661 case ARM::tBcc: in cvtThumbBranches()
4662 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
4664 case ARM::t2B: in cvtThumbBranches()
4665 case ARM::t2Bcc: in cvtThumbBranches()
4666 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
4674 case ARM::tB: { in cvtThumbBranches()
4677 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
4681 case ARM::tBcc: { in cvtThumbBranches()
4684 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
5420 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || in tryConvertingToTwoOperandForm()
5421 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
5423 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || in tryConvertingToTwoOperandForm()
5424 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
5425 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && in tryConvertingToTwoOperandForm()
5450 ((Mnemonic == "add" && Op4Reg != ARM::SP) || in tryConvertingToTwoOperandForm()
5514 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5539 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
5593 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5616 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitPredicateOperand()
5618 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( in shouldOmitPredicateOperand()
5768 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
5896 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
5912 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, in ParseInstruction()
5913 &(MRI->getRegClass(ARM::GPRPairRegClassID))); in ParseInstruction()
5928 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); in ParseInstruction()
5932 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); in ParseInstruction()
5947 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
5949 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
5991 return Inst.getOpcode() == ARM::tBKPT || in instIsBreakpoint()
5992 Inst.getOpcode() == ARM::BKPT || in instIsBreakpoint()
5993 Inst.getOpcode() == ARM::tHLT || in instIsBreakpoint()
5994 Inst.getOpcode() == ARM::HLT; in instIsBreakpoint()
6004 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetLDMRegList()
6005 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); in validatetLDMRegList()
6006 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetLDMRegList()
6027 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetSTMRegList()
6028 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetSTMRegList()
6077 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && in validateInstruction()
6078 Inst.getOpcode() != ARM::t2Bcc) in validateInstruction()
6083 case ARM::LDRD: in validateInstruction()
6084 case ARM::LDRD_PRE: in validateInstruction()
6085 case ARM::LDRD_POST: { in validateInstruction()
6089 if (RtReg == ARM::LR) in validateInstruction()
6105 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { in validateInstruction()
6117 case ARM::t2LDRDi8: in validateInstruction()
6118 case ARM::t2LDRD_PRE: in validateInstruction()
6119 case ARM::t2LDRD_POST: { in validateInstruction()
6128 case ARM::t2BXJ: { in validateInstruction()
6131 if (RmReg == ARM::SP && !hasV8Ops()) in validateInstruction()
6136 case ARM::STRD: { in validateInstruction()
6145 case ARM::STRD_PRE: in validateInstruction()
6146 case ARM::STRD_POST: { in validateInstruction()
6155 case ARM::STR_PRE_IMM: in validateInstruction()
6156 case ARM::STR_PRE_REG: in validateInstruction()
6157 case ARM::STR_POST_IMM: in validateInstruction()
6158 case ARM::STR_POST_REG: in validateInstruction()
6159 case ARM::STRH_PRE: in validateInstruction()
6160 case ARM::STRH_POST: in validateInstruction()
6161 case ARM::STRB_PRE_IMM: in validateInstruction()
6162 case ARM::STRB_PRE_REG: in validateInstruction()
6163 case ARM::STRB_POST_IMM: in validateInstruction()
6164 case ARM::STRB_POST_REG: { in validateInstruction()
6174 case ARM::LDR_PRE_IMM: in validateInstruction()
6175 case ARM::LDR_PRE_REG: in validateInstruction()
6176 case ARM::LDR_POST_IMM: in validateInstruction()
6177 case ARM::LDR_POST_REG: in validateInstruction()
6178 case ARM::LDRH_PRE: in validateInstruction()
6179 case ARM::LDRH_POST: in validateInstruction()
6180 case ARM::LDRSH_PRE: in validateInstruction()
6181 case ARM::LDRSH_POST: in validateInstruction()
6182 case ARM::LDRB_PRE_IMM: in validateInstruction()
6183 case ARM::LDRB_PRE_REG: in validateInstruction()
6184 case ARM::LDRB_POST_IMM: in validateInstruction()
6185 case ARM::LDRB_POST_REG: in validateInstruction()
6186 case ARM::LDRSB_PRE: in validateInstruction()
6187 case ARM::LDRSB_POST: { in validateInstruction()
6197 case ARM::SBFX: in validateInstruction()
6198 case ARM::UBFX: { in validateInstruction()
6208 case ARM::tLDMIA: { in validateInstruction()
6238 case ARM::LDMIA_UPD: in validateInstruction()
6239 case ARM::LDMDB_UPD: in validateInstruction()
6240 case ARM::LDMIB_UPD: in validateInstruction()
6241 case ARM::LDMDA_UPD: in validateInstruction()
6250 case ARM::t2LDMIA: in validateInstruction()
6251 case ARM::t2LDMDB: in validateInstruction()
6255 case ARM::t2STMIA: in validateInstruction()
6256 case ARM::t2STMDB: in validateInstruction()
6260 case ARM::t2LDMIA_UPD: in validateInstruction()
6261 case ARM::t2LDMDB_UPD: in validateInstruction()
6262 case ARM::t2STMIA_UPD: in validateInstruction()
6263 case ARM::t2STMDB_UPD: { in validateInstruction()
6268 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in validateInstruction()
6277 case ARM::sysLDMIA_UPD: in validateInstruction()
6278 case ARM::sysLDMDA_UPD: in validateInstruction()
6279 case ARM::sysLDMDB_UPD: in validateInstruction()
6280 case ARM::sysLDMIB_UPD: in validateInstruction()
6281 if (!listContainsReg(Inst, 3, ARM::PC)) in validateInstruction()
6286 case ARM::sysSTMIA_UPD: in validateInstruction()
6287 case ARM::sysSTMDA_UPD: in validateInstruction()
6288 case ARM::sysSTMDB_UPD: in validateInstruction()
6289 case ARM::sysSTMIB_UPD: in validateInstruction()
6292 case ARM::tMUL: { in validateInstruction()
6313 case ARM::tPOP: { in validateInstruction()
6315 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && in validateInstruction()
6323 case ARM::tPUSH: { in validateInstruction()
6325 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && in validateInstruction()
6333 case ARM::tSTMIA_UPD: { in validateInstruction()
6352 case ARM::tADDrSP: { in validateInstruction()
6363 case ARM::tB: in validateInstruction()
6367 case ARM::t2B: { in validateInstruction()
6374 case ARM::tBcc: in validateInstruction()
6378 case ARM::t2Bcc: { in validateInstruction()
6384 case ARM::MOVi16: in validateInstruction()
6385 case ARM::t2MOVi16: in validateInstruction()
6386 case ARM::t2MOVTi16: in validateInstruction()
6417 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
6418 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
6419 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
6420 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
6421 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
6422 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
6423 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; in getRealVSTOpcode()
6424 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; in getRealVSTOpcode()
6425 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; in getRealVSTOpcode()
6428 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
6429 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
6430 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
6431 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
6432 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
6434 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
6435 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
6436 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
6437 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
6438 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
6440 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; in getRealVSTOpcode()
6441 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; in getRealVSTOpcode()
6442 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; in getRealVSTOpcode()
6443 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; in getRealVSTOpcode()
6444 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; in getRealVSTOpcode()
6447 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
6448 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
6449 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
6450 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
6451 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
6452 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
6453 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
6454 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
6455 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
6456 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
6457 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; in getRealVSTOpcode()
6458 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; in getRealVSTOpcode()
6459 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; in getRealVSTOpcode()
6460 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; in getRealVSTOpcode()
6461 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; in getRealVSTOpcode()
6464 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
6465 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
6466 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
6467 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
6468 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
6469 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
6470 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
6471 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
6472 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
6473 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
6474 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
6475 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
6476 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; in getRealVSTOpcode()
6477 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; in getRealVSTOpcode()
6478 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; in getRealVSTOpcode()
6479 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; in getRealVSTOpcode()
6480 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; in getRealVSTOpcode()
6481 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; in getRealVSTOpcode()
6484 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
6485 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
6486 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
6487 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
6488 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
6489 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
6490 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
6491 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
6492 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
6493 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
6494 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; in getRealVSTOpcode()
6495 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; in getRealVSTOpcode()
6496 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; in getRealVSTOpcode()
6497 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; in getRealVSTOpcode()
6498 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; in getRealVSTOpcode()
6501 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
6502 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
6503 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
6504 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
6505 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
6506 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
6507 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
6508 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
6509 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
6510 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
6511 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
6512 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
6513 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; in getRealVSTOpcode()
6514 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; in getRealVSTOpcode()
6515 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; in getRealVSTOpcode()
6516 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; in getRealVSTOpcode()
6517 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; in getRealVSTOpcode()
6518 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; in getRealVSTOpcode()
6526 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
6527 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
6528 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
6529 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
6530 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
6531 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
6532 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; in getRealVLDOpcode()
6533 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; in getRealVLDOpcode()
6534 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; in getRealVLDOpcode()
6537 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
6538 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
6539 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
6540 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
6541 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
6542 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
6543 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
6544 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
6545 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
6546 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
6547 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; in getRealVLDOpcode()
6548 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; in getRealVLDOpcode()
6549 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; in getRealVLDOpcode()
6550 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; in getRealVLDOpcode()
6551 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; in getRealVLDOpcode()
6554 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
6555 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
6556 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
6557 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
6558 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
6559 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
6560 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
6561 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
6562 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
6563 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
6564 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
6565 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
6566 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; in getRealVLDOpcode()
6567 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; in getRealVLDOpcode()
6568 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; in getRealVLDOpcode()
6569 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; in getRealVLDOpcode()
6570 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; in getRealVLDOpcode()
6571 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; in getRealVLDOpcode()
6574 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
6575 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
6576 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
6577 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
6578 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
6579 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
6580 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
6581 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
6582 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
6583 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
6584 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; in getRealVLDOpcode()
6585 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; in getRealVLDOpcode()
6586 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; in getRealVLDOpcode()
6587 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; in getRealVLDOpcode()
6588 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; in getRealVLDOpcode()
6591 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
6592 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
6593 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
6594 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
6595 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
6596 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
6597 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
6598 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
6599 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
6600 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
6601 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
6602 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
6603 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; in getRealVLDOpcode()
6604 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; in getRealVLDOpcode()
6605 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; in getRealVLDOpcode()
6606 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; in getRealVLDOpcode()
6607 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; in getRealVLDOpcode()
6608 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; in getRealVLDOpcode()
6611 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
6612 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
6613 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
6614 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
6615 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
6616 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
6617 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
6618 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
6619 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
6620 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
6621 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; in getRealVLDOpcode()
6622 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; in getRealVLDOpcode()
6623 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; in getRealVLDOpcode()
6624 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; in getRealVLDOpcode()
6625 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; in getRealVLDOpcode()
6628 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
6629 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
6630 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
6631 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
6632 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
6633 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
6634 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
6635 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
6636 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
6637 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
6638 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
6639 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
6640 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; in getRealVLDOpcode()
6641 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; in getRealVLDOpcode()
6642 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; in getRealVLDOpcode()
6643 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; in getRealVLDOpcode()
6644 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; in getRealVLDOpcode()
6645 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; in getRealVLDOpcode()
6648 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
6649 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
6650 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
6651 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
6652 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
6653 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
6654 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
6655 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
6656 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
6657 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
6658 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
6659 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
6660 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; in getRealVLDOpcode()
6661 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; in getRealVLDOpcode()
6662 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; in getRealVLDOpcode()
6663 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; in getRealVLDOpcode()
6664 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; in getRealVLDOpcode()
6665 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; in getRealVLDOpcode()
6674 case ARM::LDRT_POST: in processInstruction()
6675 case ARM::LDRBT_POST: { in processInstruction()
6677 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM in processInstruction()
6678 : ARM::LDRBT_POST_IMM; in processInstruction()
6692 case ARM::STRT_POST: in processInstruction()
6693 case ARM::STRBT_POST: { in processInstruction()
6695 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM in processInstruction()
6696 : ARM::STRBT_POST_IMM; in processInstruction()
6710 case ARM::ADDri: { in processInstruction()
6711 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
6716 TmpInst.setOpcode(ARM::ADR); in processInstruction()
6747 case ARM::t2LDRpcrel: in processInstruction()
6753 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
6755 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
6757 case ARM::t2LDRBpcrel: in processInstruction()
6758 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
6760 case ARM::t2LDRHpcrel: in processInstruction()
6761 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
6763 case ARM::t2LDRSBpcrel: in processInstruction()
6764 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
6766 case ARM::t2LDRSHpcrel: in processInstruction()
6767 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
6770 case ARM::VST1LNdWB_register_Asm_8: in processInstruction()
6771 case ARM::VST1LNdWB_register_Asm_16: in processInstruction()
6772 case ARM::VST1LNdWB_register_Asm_32: { in processInstruction()
6790 case ARM::VST2LNdWB_register_Asm_8: in processInstruction()
6791 case ARM::VST2LNdWB_register_Asm_16: in processInstruction()
6792 case ARM::VST2LNdWB_register_Asm_32: in processInstruction()
6793 case ARM::VST2LNqWB_register_Asm_16: in processInstruction()
6794 case ARM::VST2LNqWB_register_Asm_32: { in processInstruction()
6814 case ARM::VST3LNdWB_register_Asm_8: in processInstruction()
6815 case ARM::VST3LNdWB_register_Asm_16: in processInstruction()
6816 case ARM::VST3LNdWB_register_Asm_32: in processInstruction()
6817 case ARM::VST3LNqWB_register_Asm_16: in processInstruction()
6818 case ARM::VST3LNqWB_register_Asm_32: { in processInstruction()
6840 case ARM::VST4LNdWB_register_Asm_8: in processInstruction()
6841 case ARM::VST4LNdWB_register_Asm_16: in processInstruction()
6842 case ARM::VST4LNdWB_register_Asm_32: in processInstruction()
6843 case ARM::VST4LNqWB_register_Asm_16: in processInstruction()
6844 case ARM::VST4LNqWB_register_Asm_32: { in processInstruction()
6868 case ARM::VST1LNdWB_fixed_Asm_8: in processInstruction()
6869 case ARM::VST1LNdWB_fixed_Asm_16: in processInstruction()
6870 case ARM::VST1LNdWB_fixed_Asm_32: { in processInstruction()
6888 case ARM::VST2LNdWB_fixed_Asm_8: in processInstruction()
6889 case ARM::VST2LNdWB_fixed_Asm_16: in processInstruction()
6890 case ARM::VST2LNdWB_fixed_Asm_32: in processInstruction()
6891 case ARM::VST2LNqWB_fixed_Asm_16: in processInstruction()
6892 case ARM::VST2LNqWB_fixed_Asm_32: { in processInstruction()
6912 case ARM::VST3LNdWB_fixed_Asm_8: in processInstruction()
6913 case ARM::VST3LNdWB_fixed_Asm_16: in processInstruction()
6914 case ARM::VST3LNdWB_fixed_Asm_32: in processInstruction()
6915 case ARM::VST3LNqWB_fixed_Asm_16: in processInstruction()
6916 case ARM::VST3LNqWB_fixed_Asm_32: { in processInstruction()
6938 case ARM::VST4LNdWB_fixed_Asm_8: in processInstruction()
6939 case ARM::VST4LNdWB_fixed_Asm_16: in processInstruction()
6940 case ARM::VST4LNdWB_fixed_Asm_32: in processInstruction()
6941 case ARM::VST4LNqWB_fixed_Asm_16: in processInstruction()
6942 case ARM::VST4LNqWB_fixed_Asm_32: { in processInstruction()
6966 case ARM::VST1LNdAsm_8: in processInstruction()
6967 case ARM::VST1LNdAsm_16: in processInstruction()
6968 case ARM::VST1LNdAsm_32: { in processInstruction()
6984 case ARM::VST2LNdAsm_8: in processInstruction()
6985 case ARM::VST2LNdAsm_16: in processInstruction()
6986 case ARM::VST2LNdAsm_32: in processInstruction()
6987 case ARM::VST2LNqAsm_16: in processInstruction()
6988 case ARM::VST2LNqAsm_32: { in processInstruction()
7006 case ARM::VST3LNdAsm_8: in processInstruction()
7007 case ARM::VST3LNdAsm_16: in processInstruction()
7008 case ARM::VST3LNdAsm_32: in processInstruction()
7009 case ARM::VST3LNqAsm_16: in processInstruction()
7010 case ARM::VST3LNqAsm_32: { in processInstruction()
7030 case ARM::VST4LNdAsm_8: in processInstruction()
7031 case ARM::VST4LNdAsm_16: in processInstruction()
7032 case ARM::VST4LNdAsm_32: in processInstruction()
7033 case ARM::VST4LNqAsm_16: in processInstruction()
7034 case ARM::VST4LNqAsm_32: { in processInstruction()
7057 case ARM::VLD1LNdWB_register_Asm_8: in processInstruction()
7058 case ARM::VLD1LNdWB_register_Asm_16: in processInstruction()
7059 case ARM::VLD1LNdWB_register_Asm_32: { in processInstruction()
7078 case ARM::VLD2LNdWB_register_Asm_8: in processInstruction()
7079 case ARM::VLD2LNdWB_register_Asm_16: in processInstruction()
7080 case ARM::VLD2LNdWB_register_Asm_32: in processInstruction()
7081 case ARM::VLD2LNqWB_register_Asm_16: in processInstruction()
7082 case ARM::VLD2LNqWB_register_Asm_32: { in processInstruction()
7105 case ARM::VLD3LNdWB_register_Asm_8: in processInstruction()
7106 case ARM::VLD3LNdWB_register_Asm_16: in processInstruction()
7107 case ARM::VLD3LNdWB_register_Asm_32: in processInstruction()
7108 case ARM::VLD3LNqWB_register_Asm_16: in processInstruction()
7109 case ARM::VLD3LNqWB_register_Asm_32: { in processInstruction()
7136 case ARM::VLD4LNdWB_register_Asm_8: in processInstruction()
7137 case ARM::VLD4LNdWB_register_Asm_16: in processInstruction()
7138 case ARM::VLD4LNdWB_register_Asm_32: in processInstruction()
7139 case ARM::VLD4LNqWB_register_Asm_16: in processInstruction()
7140 case ARM::VLD4LNqWB_register_Asm_32: { in processInstruction()
7171 case ARM::VLD1LNdWB_fixed_Asm_8: in processInstruction()
7172 case ARM::VLD1LNdWB_fixed_Asm_16: in processInstruction()
7173 case ARM::VLD1LNdWB_fixed_Asm_32: { in processInstruction()
7192 case ARM::VLD2LNdWB_fixed_Asm_8: in processInstruction()
7193 case ARM::VLD2LNdWB_fixed_Asm_16: in processInstruction()
7194 case ARM::VLD2LNdWB_fixed_Asm_32: in processInstruction()
7195 case ARM::VLD2LNqWB_fixed_Asm_16: in processInstruction()
7196 case ARM::VLD2LNqWB_fixed_Asm_32: { in processInstruction()
7219 case ARM::VLD3LNdWB_fixed_Asm_8: in processInstruction()
7220 case ARM::VLD3LNdWB_fixed_Asm_16: in processInstruction()
7221 case ARM::VLD3LNdWB_fixed_Asm_32: in processInstruction()
7222 case ARM::VLD3LNqWB_fixed_Asm_16: in processInstruction()
7223 case ARM::VLD3LNqWB_fixed_Asm_32: { in processInstruction()
7250 case ARM::VLD4LNdWB_fixed_Asm_8: in processInstruction()
7251 case ARM::VLD4LNdWB_fixed_Asm_16: in processInstruction()
7252 case ARM::VLD4LNdWB_fixed_Asm_32: in processInstruction()
7253 case ARM::VLD4LNqWB_fixed_Asm_16: in processInstruction()
7254 case ARM::VLD4LNqWB_fixed_Asm_32: { in processInstruction()
7285 case ARM::VLD1LNdAsm_8: in processInstruction()
7286 case ARM::VLD1LNdAsm_16: in processInstruction()
7287 case ARM::VLD1LNdAsm_32: { in processInstruction()
7304 case ARM::VLD2LNdAsm_8: in processInstruction()
7305 case ARM::VLD2LNdAsm_16: in processInstruction()
7306 case ARM::VLD2LNdAsm_32: in processInstruction()
7307 case ARM::VLD2LNqAsm_16: in processInstruction()
7308 case ARM::VLD2LNqAsm_32: { in processInstruction()
7329 case ARM::VLD3LNdAsm_8: in processInstruction()
7330 case ARM::VLD3LNdAsm_16: in processInstruction()
7331 case ARM::VLD3LNdAsm_32: in processInstruction()
7332 case ARM::VLD3LNqAsm_16: in processInstruction()
7333 case ARM::VLD3LNqAsm_32: { in processInstruction()
7358 case ARM::VLD4LNdAsm_8: in processInstruction()
7359 case ARM::VLD4LNdAsm_16: in processInstruction()
7360 case ARM::VLD4LNdAsm_32: in processInstruction()
7361 case ARM::VLD4LNqAsm_16: in processInstruction()
7362 case ARM::VLD4LNqAsm_32: { in processInstruction()
7392 case ARM::VLD3DUPdAsm_8: in processInstruction()
7393 case ARM::VLD3DUPdAsm_16: in processInstruction()
7394 case ARM::VLD3DUPdAsm_32: in processInstruction()
7395 case ARM::VLD3DUPqAsm_8: in processInstruction()
7396 case ARM::VLD3DUPqAsm_16: in processInstruction()
7397 case ARM::VLD3DUPqAsm_32: { in processInstruction()
7414 case ARM::VLD3DUPdWB_fixed_Asm_8: in processInstruction()
7415 case ARM::VLD3DUPdWB_fixed_Asm_16: in processInstruction()
7416 case ARM::VLD3DUPdWB_fixed_Asm_32: in processInstruction()
7417 case ARM::VLD3DUPqWB_fixed_Asm_8: in processInstruction()
7418 case ARM::VLD3DUPqWB_fixed_Asm_16: in processInstruction()
7419 case ARM::VLD3DUPqWB_fixed_Asm_32: { in processInstruction()
7438 case ARM::VLD3DUPdWB_register_Asm_8: in processInstruction()
7439 case ARM::VLD3DUPdWB_register_Asm_16: in processInstruction()
7440 case ARM::VLD3DUPdWB_register_Asm_32: in processInstruction()
7441 case ARM::VLD3DUPqWB_register_Asm_8: in processInstruction()
7442 case ARM::VLD3DUPqWB_register_Asm_16: in processInstruction()
7443 case ARM::VLD3DUPqWB_register_Asm_32: { in processInstruction()
7463 case ARM::VLD3dAsm_8: in processInstruction()
7464 case ARM::VLD3dAsm_16: in processInstruction()
7465 case ARM::VLD3dAsm_32: in processInstruction()
7466 case ARM::VLD3qAsm_8: in processInstruction()
7467 case ARM::VLD3qAsm_16: in processInstruction()
7468 case ARM::VLD3qAsm_32: { in processInstruction()
7485 case ARM::VLD3dWB_fixed_Asm_8: in processInstruction()
7486 case ARM::VLD3dWB_fixed_Asm_16: in processInstruction()
7487 case ARM::VLD3dWB_fixed_Asm_32: in processInstruction()
7488 case ARM::VLD3qWB_fixed_Asm_8: in processInstruction()
7489 case ARM::VLD3qWB_fixed_Asm_16: in processInstruction()
7490 case ARM::VLD3qWB_fixed_Asm_32: { in processInstruction()
7509 case ARM::VLD3dWB_register_Asm_8: in processInstruction()
7510 case ARM::VLD3dWB_register_Asm_16: in processInstruction()
7511 case ARM::VLD3dWB_register_Asm_32: in processInstruction()
7512 case ARM::VLD3qWB_register_Asm_8: in processInstruction()
7513 case ARM::VLD3qWB_register_Asm_16: in processInstruction()
7514 case ARM::VLD3qWB_register_Asm_32: { in processInstruction()
7534 case ARM::VLD4DUPdAsm_8: in processInstruction()
7535 case ARM::VLD4DUPdAsm_16: in processInstruction()
7536 case ARM::VLD4DUPdAsm_32: in processInstruction()
7537 case ARM::VLD4DUPqAsm_8: in processInstruction()
7538 case ARM::VLD4DUPqAsm_16: in processInstruction()
7539 case ARM::VLD4DUPqAsm_32: { in processInstruction()
7558 case ARM::VLD4DUPdWB_fixed_Asm_8: in processInstruction()
7559 case ARM::VLD4DUPdWB_fixed_Asm_16: in processInstruction()
7560 case ARM::VLD4DUPdWB_fixed_Asm_32: in processInstruction()
7561 case ARM::VLD4DUPqWB_fixed_Asm_8: in processInstruction()
7562 case ARM::VLD4DUPqWB_fixed_Asm_16: in processInstruction()
7563 case ARM::VLD4DUPqWB_fixed_Asm_32: { in processInstruction()
7584 case ARM::VLD4DUPdWB_register_Asm_8: in processInstruction()
7585 case ARM::VLD4DUPdWB_register_Asm_16: in processInstruction()
7586 case ARM::VLD4DUPdWB_register_Asm_32: in processInstruction()
7587 case ARM::VLD4DUPqWB_register_Asm_8: in processInstruction()
7588 case ARM::VLD4DUPqWB_register_Asm_16: in processInstruction()
7589 case ARM::VLD4DUPqWB_register_Asm_32: { in processInstruction()
7611 case ARM::VLD4dAsm_8: in processInstruction()
7612 case ARM::VLD4dAsm_16: in processInstruction()
7613 case ARM::VLD4dAsm_32: in processInstruction()
7614 case ARM::VLD4qAsm_8: in processInstruction()
7615 case ARM::VLD4qAsm_16: in processInstruction()
7616 case ARM::VLD4qAsm_32: { in processInstruction()
7635 case ARM::VLD4dWB_fixed_Asm_8: in processInstruction()
7636 case ARM::VLD4dWB_fixed_Asm_16: in processInstruction()
7637 case ARM::VLD4dWB_fixed_Asm_32: in processInstruction()
7638 case ARM::VLD4qWB_fixed_Asm_8: in processInstruction()
7639 case ARM::VLD4qWB_fixed_Asm_16: in processInstruction()
7640 case ARM::VLD4qWB_fixed_Asm_32: { in processInstruction()
7661 case ARM::VLD4dWB_register_Asm_8: in processInstruction()
7662 case ARM::VLD4dWB_register_Asm_16: in processInstruction()
7663 case ARM::VLD4dWB_register_Asm_32: in processInstruction()
7664 case ARM::VLD4qWB_register_Asm_8: in processInstruction()
7665 case ARM::VLD4qWB_register_Asm_16: in processInstruction()
7666 case ARM::VLD4qWB_register_Asm_32: { in processInstruction()
7688 case ARM::VST3dAsm_8: in processInstruction()
7689 case ARM::VST3dAsm_16: in processInstruction()
7690 case ARM::VST3dAsm_32: in processInstruction()
7691 case ARM::VST3qAsm_8: in processInstruction()
7692 case ARM::VST3qAsm_16: in processInstruction()
7693 case ARM::VST3qAsm_32: { in processInstruction()
7710 case ARM::VST3dWB_fixed_Asm_8: in processInstruction()
7711 case ARM::VST3dWB_fixed_Asm_16: in processInstruction()
7712 case ARM::VST3dWB_fixed_Asm_32: in processInstruction()
7713 case ARM::VST3qWB_fixed_Asm_8: in processInstruction()
7714 case ARM::VST3qWB_fixed_Asm_16: in processInstruction()
7715 case ARM::VST3qWB_fixed_Asm_32: { in processInstruction()
7734 case ARM::VST3dWB_register_Asm_8: in processInstruction()
7735 case ARM::VST3dWB_register_Asm_16: in processInstruction()
7736 case ARM::VST3dWB_register_Asm_32: in processInstruction()
7737 case ARM::VST3qWB_register_Asm_8: in processInstruction()
7738 case ARM::VST3qWB_register_Asm_16: in processInstruction()
7739 case ARM::VST3qWB_register_Asm_32: { in processInstruction()
7759 case ARM::VST4dAsm_8: in processInstruction()
7760 case ARM::VST4dAsm_16: in processInstruction()
7761 case ARM::VST4dAsm_32: in processInstruction()
7762 case ARM::VST4qAsm_8: in processInstruction()
7763 case ARM::VST4qAsm_16: in processInstruction()
7764 case ARM::VST4qAsm_32: { in processInstruction()
7783 case ARM::VST4dWB_fixed_Asm_8: in processInstruction()
7784 case ARM::VST4dWB_fixed_Asm_16: in processInstruction()
7785 case ARM::VST4dWB_fixed_Asm_32: in processInstruction()
7786 case ARM::VST4qWB_fixed_Asm_8: in processInstruction()
7787 case ARM::VST4qWB_fixed_Asm_16: in processInstruction()
7788 case ARM::VST4qWB_fixed_Asm_32: { in processInstruction()
7809 case ARM::VST4dWB_register_Asm_8: in processInstruction()
7810 case ARM::VST4dWB_register_Asm_16: in processInstruction()
7811 case ARM::VST4dWB_register_Asm_32: in processInstruction()
7812 case ARM::VST4qWB_register_Asm_8: in processInstruction()
7813 case ARM::VST4qWB_register_Asm_16: in processInstruction()
7814 case ARM::VST4qWB_register_Asm_32: { in processInstruction()
7836 case ARM::t2LSLri: in processInstruction()
7837 case ARM::t2LSRri: in processInstruction()
7838 case ARM::t2ASRri: { in processInstruction()
7841 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
7847 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
7848 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
7849 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
7867 case ARM::t2MOVsr: in processInstruction()
7868 case ARM::t2MOVSsr: { in processInstruction()
7877 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) in processInstruction()
7883 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
7884 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
7885 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
7886 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
7892 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
7899 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
7903 case ARM::t2MOVsi: in processInstruction()
7904 case ARM::t2MOVSsi: { in processInstruction()
7911 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) in processInstruction()
7917 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
7918 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
7919 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
7920 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
7921 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
7929 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
7931 if (newOpc != ARM::t2RRX) in processInstruction()
7937 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
7942 case ARM::ASRr: in processInstruction()
7943 case ARM::LSRr: in processInstruction()
7944 case ARM::LSLr: in processInstruction()
7945 case ARM::RORr: { in processInstruction()
7949 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
7950 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
7951 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
7952 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
7956 TmpInst.setOpcode(ARM::MOVsr); in processInstruction()
7967 case ARM::ASRi: in processInstruction()
7968 case ARM::LSRi: in processInstruction()
7969 case ARM::LSLi: in processInstruction()
7970 case ARM::RORi: { in processInstruction()
7974 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
7975 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
7976 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
7977 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
7981 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; in processInstruction()
7990 if (Opc == ARM::MOVsi) in processInstruction()
7998 case ARM::RRXi: { in processInstruction()
8001 TmpInst.setOpcode(ARM::MOVsi); in processInstruction()
8011 case ARM::t2LDMIA_UPD: { in processInstruction()
8017 TmpInst.setOpcode(ARM::t2LDR_POST); in processInstruction()
8027 case ARM::t2STMDB_UPD: { in processInstruction()
8033 TmpInst.setOpcode(ARM::t2STR_PRE); in processInstruction()
8043 case ARM::LDMIA_UPD: in processInstruction()
8049 TmpInst.setOpcode(ARM::LDR_POST_IMM); in processInstruction()
8061 case ARM::STMDB_UPD: in processInstruction()
8067 TmpInst.setOpcode(ARM::STR_PRE_IMM); in processInstruction()
8077 case ARM::t2ADDri12: in processInstruction()
8083 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
8086 case ARM::t2SUBri12: in processInstruction()
8092 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
8095 case ARM::tADDi8: in processInstruction()
8101 Inst.setOpcode(ARM::tADDi3); in processInstruction()
8105 case ARM::tSUBi8: in processInstruction()
8111 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
8115 case ARM::t2ADDri: in processInstruction()
8116 case ARM::t2SUBri: { in processInstruction()
8124 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || in processInstruction()
8130 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
8131 ARM::tADDi8 : ARM::tSUBi8); in processInstruction()
8141 case ARM::t2ADDrr: { in processInstruction()
8160 TmpInst.setOpcode(ARM::tADDhirr); in processInstruction()
8169 case ARM::tADDrSP: { in processInstruction()
8173 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
8179 case ARM::tB: in processInstruction()
8182 Inst.setOpcode(ARM::tBcc); in processInstruction()
8186 case ARM::t2B: in processInstruction()
8189 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
8193 case ARM::t2Bcc: in processInstruction()
8196 Inst.setOpcode(ARM::t2B); in processInstruction()
8200 case ARM::tBcc: in processInstruction()
8203 Inst.setOpcode(ARM::tB); in processInstruction()
8207 case ARM::tLDMIA: { in processInstruction()
8222 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
8232 case ARM::tSTMIA_UPD: { in processInstruction()
8241 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
8246 case ARM::tPOP: { in processInstruction()
8251 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
8254 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
8256 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8257 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8260 case ARM::tPUSH: { in processInstruction()
8262 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
8265 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
8267 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8268 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8271 case ARM::t2MOVi: { in processInstruction()
8277 Inst.getOperand(4).getReg() == ARM::CPSR) || in processInstruction()
8283 TmpInst.setOpcode(ARM::tMOVi8); in processInstruction()
8294 case ARM::t2MOVr: { in processInstruction()
8300 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
8305 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); in processInstruction()
8315 case ARM::t2SXTH: in processInstruction()
8316 case ARM::t2SXTB: in processInstruction()
8317 case ARM::t2UXTH: in processInstruction()
8318 case ARM::t2UXTB: { in processInstruction()
8329 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
8330 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
8331 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
8332 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
8346 case ARM::MOVsi: { in processInstruction()
8354 TmpInst.setOpcode(ARM::MOVr); in processInstruction()
8365 case ARM::ANDrsi: in processInstruction()
8366 case ARM::ORRrsi: in processInstruction()
8367 case ARM::EORrsi: in processInstruction()
8368 case ARM::BICrsi: in processInstruction()
8369 case ARM::SUBrsi: in processInstruction()
8370 case ARM::ADDrsi: { in processInstruction()
8376 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; in processInstruction()
8377 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; in processInstruction()
8378 case ARM::EORrsi: newOpc = ARM::EORrr; break; in processInstruction()
8379 case ARM::BICrsi: newOpc = ARM::BICrr; break; in processInstruction()
8380 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; in processInstruction()
8381 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; in processInstruction()
8400 case ARM::ITasm: in processInstruction()
8401 case ARM::t2IT: { in processInstruction()
8425 case ARM::t2LSLrr: in processInstruction()
8426 case ARM::t2LSRrr: in processInstruction()
8427 case ARM::t2ASRrr: in processInstruction()
8428 case ARM::t2SBCrr: in processInstruction()
8429 case ARM::t2RORrr: in processInstruction()
8430 case ARM::t2BICrr: in processInstruction()
8436 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || in processInstruction()
8437 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && in processInstruction()
8444 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; in processInstruction()
8445 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; in processInstruction()
8446 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; in processInstruction()
8447 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; in processInstruction()
8448 case ARM::t2RORrr: NewOpc = ARM::tROR; break; in processInstruction()
8449 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; in processInstruction()
8464 case ARM::t2ANDrr: in processInstruction()
8465 case ARM::t2EORrr: in processInstruction()
8466 case ARM::t2ADCrr: in processInstruction()
8467 case ARM::t2ORRrr: in processInstruction()
8476 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || in processInstruction()
8477 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && in processInstruction()
8484 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; in processInstruction()
8485 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; in processInstruction()
8486 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; in processInstruction()
8487 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; in processInstruction()
8528 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
8532 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
8535 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
8541 if (Opc == ARM::tADDhirr && !hasV6MOps() && in checkTargetMatchPredicate()
8546 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()
8553 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { in checkTargetMatchPredicate()
8555 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops()) in checkTargetMatchPredicate()
8557 else if (Inst.getOperand(I).getReg() == ARM::PC) in checkTargetMatchPredicate()
8615 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
9039 unsigned ID = ARM::parseArch(Arch); in parseDirectiveArch()
9041 if (ID == ARM::AK_INVALID) { in parseDirectiveArch()
9048 STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str()); in parseDirectiveArch()
9192 unsigned ID = ARM::parseFPU(FPU); in parseDirectiveFPU()
9194 if (!ARM::getFPUFeatures(ID, Features)) { in parseDirectiveFPU()
9368 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) { in parseDirectiveSetFP()
9643 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) { in parseDirectivePersonalityIndex()
9770 if (UC.getFPReg() != ARM::SP) { in parseDirectiveMovSP()
9784 if (SPReg == ARM::SP || SPReg == ARM::PC) { in parseDirectiveMovSP()
9839 unsigned ID = ARM::parseArch(Arch); in parseDirectiveObjectArch()
9841 if (ID == ARM::AK_INVALID) { in parseDirectiveObjectArch()
9924 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
9925 { ARM::AEK_CRYPTO, Feature_HasV8,
9926 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9927 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
9928 { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
9929 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
9930 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
9931 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9932 { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
9934 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
9935 { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
9937 { ARM::AEK_OS, Feature_None, {} },
9938 { ARM::AEK_IWMMXT, Feature_None, {} },
9939 { ARM::AEK_IWMMXT2, Feature_None, {} },
9940 { ARM::AEK_MAVERICK, Feature_None, {} },
9941 { ARM::AEK_XSCALE, Feature_None, {} },
9964 unsigned FeatureKind = ARM::parseArchExt(Name); in parseDirectiveArchExtension()
9965 if (FeatureKind == ARM::AEK_INVALID) in parseDirectiveArchExtension()
10024 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) in validateTargetOperandClass()
10029 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) in validateTargetOperandClass()