203   if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||  in CC_Hexagon_VarArg()
348       (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||  in CC_HexagonVector()
371       (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||  in CC_HexagonVector()
416              LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||  in RetCC_Hexagon()
418     LocVT = MVT::v32i32;  in RetCC_Hexagon()
419     ValVT = MVT::v32i32;  in RetCC_Hexagon()
436   if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {  in RetCC_Hexagon()
488   } else if (LocVT == MVT::v32i32) {  in RetCC_HexagonVector()
546           ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 ||  in IsHvxVectorType()
885     (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||  in getIndexedAddressParts()
1089                ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||  in LowerFormalArguments()
1097       } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||  in LowerFormalArguments()
1572       addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);  in HexagonTargetLowering()
1578       addRegisterClass(MVT::v32i32,  &Hexagon::VectorRegs128BRegClass);  in HexagonTargetLowering()
1814       setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32,  Custom);  in HexagonTargetLowering()
1885     for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {  in HexagonTargetLowering()
2366       MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;  in LowerCONCAT_VECTORS()
2367       MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;  in LowerCONCAT_VECTORS()
2685        case MVT::v32i32:  in getRegForInlineAsmConstraint()
2834   case MVT::v32i32:  in findRepresentativeClass()