Lines Matching refs:Rs
131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
175 bits<5> Rs;
180 let Inst{20-16} = Rs;
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
202 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
203 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
205 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
210 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
211 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
224 bits<5> Rs;
230 let Inst{20-16} = Rs;
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
246 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
257 bits<5> Rs;
264 let Inst{20-16} = Rs;
273 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
274 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
275 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
276 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
298 bits<5> Rs;
304 let Inst{20-16} = Rs;
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
312 "$Rdd = combine($Rs, #$s8)">;
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
316 "$Rdd = combine(#$s8, $Rs)">;
358 def Zext64: OutPatFrag<(ops node:$Rs),
359 (i64 (A4_combineir 0, (i32 $Rs)))>;
360 def Sext64: OutPatFrag<(ops node:$Rs),
361 (i64 (A2_sxtw (i32 $Rs)))>;
373 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
374 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
375 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
376 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
388 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
635 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
637 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
653 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
654 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
857 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
858 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
861 bits<5> Rs;
873 let Inst{20-16} = Rs;
888 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
891 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
894 bits<5> Rs;
910 let Inst{20-16} = Rs;
924 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
925 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
928 bits<5> Rs;
936 let Inst{20-16} = Rs;
951 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
953 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
956 bits<5> Rs;
969 let Inst{20-16} = Rs;
1039 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1041 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1067 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1068 mnemonic#"($Rs+#$offset)=#$S8",
1071 bits<5> Rs;
1085 let Inst{20-16} = Rs;
1096 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1098 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1102 bits<5> Rs;
1120 let Inst{20-16} = Rs;
1217 // memh(Rs+#s11:1)=Rt.H
1218 // memh(Rs+Ru<<#u2)=Rt.H
1234 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1751 (ins IntRegs:$Rs),
1752 "hintjr($Rs)"> {
1753 bits<5> Rs;
1756 let Inst{20-16} = Rs;
1870 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1871 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1872 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1873 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1876 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1877 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1879 bits<5> Rs;
1884 let Inst{20-16} = Rs;
1890 // Rd=add(Rs,add(Ru,#s6))
1894 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1895 "$Rd = add($Rs, add($Ru, #$s6))" ,
1896 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1900 bits<5> Rs;
1908 let Inst{20-16} = Rs;
1918 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1919 "$Rd = add($Rs, sub(#$s6, $Ru))",
1922 bits<5> Rs;
1930 let Inst{20-16} = Rs;
1937 // Rd=add(Rs,sub(#s6,Ru))
1942 // Rd=sub(add(Rs,#s6),Ru)
1947 // Rd=add(sub(Rs,Ru),#s6)
1962 // Rd=extract(Rs,Rtt)
1963 // Rd=extract(Rs,#u5,#U5)
2121 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2122 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2124 bits<5> Rs;
2129 let Inst{20-16} = Rs;
2137 (ins IntRegs:$Rs, IntRegs:$Rt),
2138 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2140 bits<5> Rs;
2146 let Inst{20-16} = Rs;
2153 (ins IntRegs:$Rs, IntRegs:$Rt),
2154 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2156 bits<5> Rs;
2162 let Inst{20-16} = Rs;
2169 (ins IntRegs:$Rs, IntRegs:$Rt),
2170 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2172 bits<5> Rs;
2177 let Inst{20-16} = Rs;
2185 (ins IntRegs:$Rs, IntRegs:$Rt),
2186 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2188 bits<5> Rs;
2194 let Inst{12-8} = Rs;
2199 // Rx[&|]=xor(Rs,Rt)
2203 // Rx[&|^]=or(Rs,Rt)
2210 // Rx[&|^]=and(Rs,Rt)
2217 // Rx[&|^]=and(Rs,~Rt)
2245 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2246 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2248 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
2251 bits<5> Rs;
2258 let Inst{20-16} = Rs;
2271 // Rd=modwrap(Rs,Rt)
2273 // Rd=cround(Rs,#u5)
2274 // Rd=cround(Rs,Rt)
2275 // Rd=round(Rs,#u5)[:sat]
2276 // Rd=round(Rs,Rt)[:sat]
2339 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2340 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2341 bits<5> Rs;
2347 let Inst{20-16} = Rs;
2354 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2355 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2356 bits<5> Rs;
2362 let Inst{20-16} = Rs;
2374 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2375 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2376 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2377 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2384 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2385 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2388 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2389 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2401 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2402 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2403 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2404 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2405 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2406 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2416 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2420 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2421 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2423 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2427 bits<5> Rs;
2435 let Inst{20-16} = Rs;
2442 // Rd=add(#u6,mpyi(Rs,Rt))
2446 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2447 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2449 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
2453 bits<5> Rs;
2460 let Inst{20-16} = Rs;
2502 // Rx=add(Ru,mpyi(Rx,Rs))
2505 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2506 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2508 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2512 bits<5> Rs;
2519 let Inst{20-16} = Rs;
2541 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2545 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2550 // Rdd=vpmpyh(Rs,Rt)
2553 // Rxx^=vpmpyh(Rs,Rt)
2557 // Rdd=pmpyw(Rs,Rt)
2560 // Rxx^=pmpyw(Rs,Rt)
2685 // Rd=[cround|round](Rs,Rt)
2691 // Rd=round(Rs,Rt):sat
2964 // mem[bh](Rs+#0) += #U5
2965 // mem[bh](Rs+#u6) += #U5
3010 // mem[bh](Rs+#0) += #m5
3011 // mem[bh](Rs+#u6) += #m5
3049 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3050 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
3057 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
3064 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3086 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
3087 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
3092 // memw(Rs+#0) = [clrbit|setbit](#U5)
3093 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3103 // mem[bhw](Rs+#0) [+-&|]= Rt
3104 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3110 // mem[bhw](Rs+#0) [+-&|]= Rt
3115 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3167 // Pd=cmpb.eq(Rs,#u8)
3184 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3200 // zext( setult ( and(Rs, 255), u8))
3799 def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3800 def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3801 def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3818 // memw(Rs+#u6:2)=#S8
3951 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3952 "$Pd=boundscheck($Rs,$Rtt)">;
3957 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3958 "$Pd = tlbmatch($Rs, $Rt)",
3961 bits<5> Rs;
3966 let Inst{20-16} = Rs;
3983 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
3984 "dcfetch($Rs + #$u11_3)",
3985 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
3987 bits<5> Rs;
3992 let Inst{20-16} = Rs;
4006 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4007 ""#px#" = tstbit($Rs, #0); if ("
4010 bits<4> Rs;
4026 let Inst{19-16} = Rs;
4052 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4053 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4056 bits<4> Rs;
4072 let Inst{19-16} = Rs;
4106 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4107 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4110 bits<4> Rs;
4130 let Inst{19-16} = Rs;
4161 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4162 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4165 bits<4> Rs;
4182 let Inst{19-16} = Rs;
4235 (ins IntRegs:$Rs, brtarget:$r9_2),
4236 "$Rd = $Rs ; jump $r9_2"> {
4238 bits<4> Rs;
4245 let Inst{19-16} = Rs;