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Lines Matching refs:Amt

6651   SDValue Amt = Op.getOperand(2);  in LowerSHL_PARTS()  local
6652 EVT AmtVT = Amt.getValueType(); in LowerSHL_PARTS()
6655 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSHL_PARTS()
6656 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS()
6659 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSHL_PARTS()
6663 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); in LowerSHL_PARTS()
6680 SDValue Amt = Op.getOperand(2); in LowerSRL_PARTS() local
6681 EVT AmtVT = Amt.getValueType(); in LowerSRL_PARTS()
6684 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSRL_PARTS()
6685 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS()
6688 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSRL_PARTS()
6692 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); in LowerSRL_PARTS()
6708 SDValue Amt = Op.getOperand(2); in LowerSRA_PARTS() local
6709 EVT AmtVT = Amt.getValueType(); in LowerSRA_PARTS()
6712 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSRA_PARTS()
6713 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRA_PARTS()
6716 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSRA_PARTS()
6719 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); in LowerSRA_PARTS()
6788 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, in BuildVSLDOI() argument
6796 Ops[i] = i + Amt; in BuildVSLDOI()
7068 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1; in LowerBUILD_VECTOR() local
7069 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl); in LowerBUILD_VECTOR()
7074 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2; in LowerBUILD_VECTOR() local
7075 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl); in LowerBUILD_VECTOR()
7080 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3; in LowerBUILD_VECTOR() local
7081 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl); in LowerBUILD_VECTOR()