Lines Matching refs:Pseudo
1016 // Pseudo-instructions:
1020 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1022 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt…
1026 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1031 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1034 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1044 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1048 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1052 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1055 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1058 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1064 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1067 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1070 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1073 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1076 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1085 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1087 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1094 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1096 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1122 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1125 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1317 def TCRETURNdi :Pseudo< (outs),
1324 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1329 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1357 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1362 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1369 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1444 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1447 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1450 def ATOMIC_LOAD_AND_I8 : Pseudo<
1453 def ATOMIC_LOAD_OR_I8 : Pseudo<
1456 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1459 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1462 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1465 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1468 def ATOMIC_LOAD_AND_I16 : Pseudo<
1471 def ATOMIC_LOAD_OR_I16 : Pseudo<
1474 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1477 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1480 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1483 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1486 def ATOMIC_LOAD_AND_I32 : Pseudo<
1489 def ATOMIC_LOAD_OR_I32 : Pseudo<
1492 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1495 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1499 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1502 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1505 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1509 def ATOMIC_SWAP_I8 : Pseudo<
1512 def ATOMIC_SWAP_I16 : Pseudo<
1515 def ATOMIC_SWAP_I32 : Pseudo<
2237 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2292 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2298 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2320 // Pseudo instruction to perform FADD in round-to-zero mode.
2322 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2656 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2662 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2665 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2672 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2680 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2688 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2695 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2703 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2712 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2719 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2723 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2730 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2736 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
3407 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3410 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3414 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3417 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3618 // Pseudo-instructions for alternate assembly syntax (never used by codegen).