Lines Matching refs:ins
253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
277 (outs RC:$dst), (ins MEMrr:$addr),
281 (outs RC:$dst), (ins MEMri:$addr),
290 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
304 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
306 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
309 (ins MEMrr:$addr, i8imm:$asi),
316 (outs), (ins MEMrr:$addr, RC:$rd),
320 (outs), (ins MEMri:$addr, RC:$rd),
329 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
344 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
345 : InstSP<outs, ins, asmstr, pattern> {
352 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
356 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
359 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
366 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
370 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
381 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
385 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
390 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
395 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
403 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
408 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
412 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
416 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
451 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
453 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
457 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
459 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
492 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
494 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
498 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
500 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
509 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
513 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
517 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
525 (outs IntRegs:$rd), (ins i32imm:$imm22),
532 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
538 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
542 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
548 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
557 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
561 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
584 (outs IntRegs:$dst), (ins MEMri:$addr),
611 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
615 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
653 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
654 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
662 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
668 class BranchSP<dag ins, string asmstr, list<dag> pattern>
669 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
672 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
673 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
677 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
680 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
683 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
686 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
698 (outs), (ins MEMrr:$ptr),
702 (outs), (ins MEMri:$ptr),
708 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
711 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
723 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
724 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
727 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
728 : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
732 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
735 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
738 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
741 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
748 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
751 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
763 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
773 (outs), (ins MEMrr:$ptr, variable_ops),
777 (outs), (ins MEMri:$ptr, variable_ops),
788 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
790 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
799 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
803 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
810 def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
812 def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
819 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
822 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
831 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
836 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
843 (outs IntRegs:$rd), (ins),
848 (outs IntRegs:$rd), (ins),
853 (outs IntRegs:$rd), (ins),
859 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
862 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
869 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
872 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
878 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
881 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
887 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
890 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
897 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
902 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
907 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
909 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
916 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
923 (outs FPRegs:$rd), (ins FPRegs:$rs2),
927 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
931 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
938 (outs FPRegs:$rd), (ins FPRegs:$rs2),
942 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
946 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
953 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
957 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
962 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
966 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
971 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
976 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
983 (outs FPRegs:$rd), (ins FPRegs:$rs2),
986 (outs FPRegs:$rd), (ins FPRegs:$rs2),
990 (outs FPRegs:$rd), (ins FPRegs:$rs2),
997 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1001 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1005 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1014 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1018 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1022 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1028 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1032 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1036 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1044 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1048 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1052 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1058 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1063 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1070 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1074 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1078 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1092 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1096 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1100 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1112 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1119 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1126 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1145 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1151 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1160 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1165 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1174 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1179 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1184 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1193 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1198 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1203 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1214 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1217 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1221 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1225 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1230 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1234 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1242 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1245 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1248 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1254 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1257 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1260 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1270 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1274 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1278 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1282 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1286 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1297 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1303 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1314 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1335 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1342 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1345 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),