Lines Matching refs:rd
253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
254 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
255 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
258 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
267 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
270 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
316 (outs), (ins MEMrr:$addr, RC:$rd),
317 !strconcat(OpcStr, " $rd, [$addr]"),
318 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
320 (outs), (ins MEMri:$addr, RC:$rd),
321 !strconcat(OpcStr, " $rd, [$addr]"),
322 [(OpNode Ty:$rd, ADDRri:$addr)]>;
329 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
330 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
365 let rd = 0, rs1 = 0, rs2 = 0 in
369 let rd = 0, rs1 = 1, simm13 = 3 in
450 let rd = 0 in {
456 let rd = 1 in {
491 let rd = 0 in {
497 let rd = 1 in {
525 (outs IntRegs:$rd), (ins i32imm:$imm22),
526 "sethi $imm22, $rd",
527 [(set i32:$rd, SETHIimm:$imm22)]>;
531 let rd = 0, imm22 = 0 in
538 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
539 "andn $rs1, $rs2, $rd",
540 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
542 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
543 "andn $rs1, $simm13, $rd", []>;
548 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
549 "orn $rs1, $rs2, $rd",
550 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
553 "orn $rs1, $simm13, $rd", []>;
557 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
558 "xnor $rs1, $rs2, $rd",
559 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
561 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
562 "xnor $rs1, $simm13, $rd", []>;
609 let Defs = [ICC], rd = 0 in {
696 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
771 let isCodeGenOnly = 1, rd = 15 in {
798 let rd = 0, rs1 = 15 in
802 let rd = 0, rs1 = 31 in
809 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
830 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
836 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
837 "rd $rs1, $rd", []>;
843 (outs IntRegs:$rd), (ins),
844 "rd %psr, $rd", []>;
848 (outs IntRegs:$rd), (ins),
849 "rd %wim, $rd", []>;
853 (outs IntRegs:$rd), (ins),
854 "rd %tbr, $rd", []>;
859 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
860 "wr $rs1, $rs2, $rd", []>;
862 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
863 "wr $rs1, $simm13, $rd", []>;
867 let Defs = [PSR], rd=0 in {
876 let Defs = [WIM], rd=0 in {
885 let Defs = [TBR], rd=0 in {
896 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
901 let rd = 0 in
906 let rd = 0 in {
923 (outs FPRegs:$rd), (ins FPRegs:$rs2),
924 "fitos $rs2, $rd",
925 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
927 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
928 "fitod $rs2, $rd",
929 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
931 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
932 "fitoq $rs2, $rd",
933 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
938 (outs FPRegs:$rd), (ins FPRegs:$rs2),
939 "fstoi $rs2, $rd",
940 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
942 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
943 "fdtoi $rs2, $rd",
944 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
946 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
947 "fqtoi $rs2, $rd",
948 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
953 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
954 "fstod $rs2, $rd",
955 [(set f64:$rd, (fextend f32:$rs2))]>;
957 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
958 "fstoq $rs2, $rd",
959 [(set f128:$rd, (fextend f32:$rs2))]>,
962 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
963 "fdtos $rs2, $rd",
964 [(set f32:$rd, (fround f64:$rs2))]>;
966 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
967 "fdtoq $rs2, $rd",
968 [(set f128:$rd, (fextend f64:$rs2))]>,
971 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
972 "fqtos $rs2, $rd",
973 [(set f32:$rd, (fround f128:$rs2))]>,
976 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
977 "fqtod $rs2, $rd",
978 [(set f64:$rd, (fround f128:$rs2))]>,
983 (outs FPRegs:$rd), (ins FPRegs:$rs2),
984 "fmovs $rs2, $rd", []>;
986 (outs FPRegs:$rd), (ins FPRegs:$rs2),
987 "fnegs $rs2, $rd",
988 [(set f32:$rd, (fneg f32:$rs2))]>;
990 (outs FPRegs:$rd), (ins FPRegs:$rs2),
991 "fabss $rs2, $rd",
992 [(set f32:$rd, (fabs f32:$rs2))]>;
997 (outs FPRegs:$rd), (ins FPRegs:$rs2),
998 "fsqrts $rs2, $rd",
999 [(set f32:$rd, (fsqrt f32:$rs2))]>;
1001 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1002 "fsqrtd $rs2, $rd",
1003 [(set f64:$rd, (fsqrt f64:$rs2))]>;
1005 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1006 "fsqrtq $rs2, $rd",
1007 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1014 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1015 "fadds $rs1, $rs2, $rd",
1016 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
1018 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1019 "faddd $rs1, $rs2, $rd",
1020 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
1022 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1023 "faddq $rs1, $rs2, $rd",
1024 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1028 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1029 "fsubs $rs1, $rs2, $rd",
1030 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
1032 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1033 "fsubd $rs1, $rs2, $rd",
1034 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
1036 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1037 "fsubq $rs1, $rs2, $rd",
1038 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1044 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1045 "fmuls $rs1, $rs2, $rd",
1046 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
1048 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1049 "fmuld $rs1, $rs2, $rd",
1050 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
1052 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1053 "fmulq $rs1, $rs2, $rd",
1054 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1058 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1059 "fsmuld $rs1, $rs2, $rd",
1060 [(set f64:$rd, (fmul (fextend f32:$rs1),
1063 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1064 "fdmulq $rs1, $rs2, $rd",
1065 [(set f128:$rd, (fmul (fextend f64:$rs1),
1070 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1071 "fdivs $rs1, $rs2, $rd",
1072 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
1074 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1075 "fdivd $rs1, $rs2, $rd",
1076 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
1078 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1079 "fdivq $rs1, $rs2, $rd",
1080 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1090 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1111 (outs IntRegs:$rd),
1113 "add $rs1, $rs2, $rd, $sym",
1114 [(set i32:$rd,
1140 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1144 : F4_1<0b101100, (outs IntRegs:$rd),
1146 "mov$cond %icc, $rs2, $rd",
1147 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1150 : F4_2<0b101100, (outs IntRegs:$rd),
1152 "mov$cond %icc, $simm11, $rd",
1153 [(set i32:$rd,
1159 : F4_1<0b101100, (outs IntRegs:$rd),
1161 "mov$cond %fcc0, $rs2, $rd",
1162 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1164 : F4_2<0b101100, (outs IntRegs:$rd),
1166 "mov$cond %fcc0, $simm11, $rd",
1167 [(set i32:$rd,
1173 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1175 "fmovs$cond %icc, $rs2, $rd",
1176 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1178 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1180 "fmovd$cond %icc, $rs2, $rd",
1181 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1183 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1185 "fmovq$cond %icc, $rs2, $rd",
1186 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1192 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1194 "fmovs$cond %fcc0, $rs2, $rd",
1195 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1197 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1199 "fmovd$cond %fcc0, $rs2, $rd",
1200 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1202 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1204 "fmovq$cond %fcc0, $rs2, $rd",
1205 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1214 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1215 "fmovd $rs2, $rd", []>;
1217 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1218 "fmovq $rs2, $rd", []>,
1221 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1222 "fnegd $rs2, $rd",
1223 [(set f64:$rd, (fneg f64:$rs2))]>;
1225 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1226 "fnegq $rs2, $rd",
1227 [(set f128:$rd, (fneg f128:$rs2))]>,
1230 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1231 "fabsd $rs2, $rd",
1232 [(set f64:$rd, (fabs f64:$rs2))]>;
1234 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1235 "fabsq $rs2, $rd",
1236 [(set f128:$rd, (fabs f128:$rs2))]>,
1242 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1243 "fcmps $rd, $rs1, $rs2", []>;
1245 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1246 "fcmpd $rd, $rs1, $rs2", []>;
1248 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1249 "fcmpq $rd, $rs1, $rs2", []>,
1254 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1255 "fcmpes $rd, $rs1, $rs2", []>;
1257 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1258 "fcmped $rd, $rs1, $rs2", []>;
1260 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1261 "fcmpeq $rd, $rs1, $rs2", []>,
1267 let Constraints = "$f = $rd", intcc = 0 in {
1269 : F4_1<0b101100, (outs IntRegs:$rd),
1271 "mov$cond $cc, $rs2, $rd", []>;
1273 : F4_2<0b101100, (outs IntRegs:$rd),
1275 "mov$cond $cc, $simm11, $rd", []>;
1277 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1279 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1281 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1283 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1285 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1287 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1289 } // Constraints = "$f = $rd", ...
1297 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1298 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1302 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1312 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1314 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1316 "cas [$rs1], $rs2, $rd",
1317 [(set i32:$rd,
1335 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1336 "rdpr $rs1, $rd", []>;
1342 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1343 "wrpr $rs1, $rs2, $rd", []>;
1345 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1346 "wrpr $rs1, $simm13, $rd", []>;