700     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);  in X86TargetLowering()
791   setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v1i64, Expand);  in X86TargetLowering()
858     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);  in X86TargetLowering()
859     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);  in X86TargetLowering()
860     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);  in X86TargetLowering()
906     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2f64, Custom);  in X86TargetLowering()
910       setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);  in X86TargetLowering()
1009     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);  in X86TargetLowering()
1010     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);  in X86TargetLowering()
1011     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);  in X86TargetLowering()
1012     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);  in X86TargetLowering()
1022       setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);  in X86TargetLowering()
1283       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
1482     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i1, Custom);  in X86TargetLowering()
1483     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i1, Custom);  in X86TargetLowering()
1600         setOperationAction(ISD::INSERT_VECTOR_ELT,   VT, Custom);  in X86TargetLowering()
1656     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v32i1, Custom);  in X86TargetLowering()
1657     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v64i1, Custom);  in X86TargetLowering()
1658     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v32i16, Custom);  in X86TargetLowering()
1659     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v64i8, Custom);  in X86TargetLowering()
5111         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,  in LowerBuildVectorv16i8()
5148         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,  in LowerBuildVectorv16i8()
5178       V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,  in LowerBuildVectorv8i16()
5696   if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))  in buildFromShuffleMostly()
5756     NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),  in buildFromShuffleMostly()
5857     DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,  in LowerBUILD_VECTORvXi1()
6377           return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,  in LowerBUILD_VECTOR()
6571         Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,  in LowerBUILD_VECTOR()
11708     SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,  in InsertBitToMaskVector()
11767     V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,  in LowerINSERT_VECTOR_ELT()
15387       Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,  in LowerExtendedLoad()
18510         } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {  in LowerScalarVariableShift()
20067   case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);  in LowerOperation()