748     setOperationAction(ISD::SIGN_EXTEND, VT, Expand);  in X86TargetLowering()
1136     setOperationAction(ISD::SIGN_EXTEND,       MVT::v4i64, Custom);  in X86TargetLowering()
1137     setOperationAction(ISD::SIGN_EXTEND,       MVT::v8i32, Custom);  in X86TargetLowering()
1138     setOperationAction(ISD::SIGN_EXTEND,       MVT::v16i16, Custom);  in X86TargetLowering()
1448     setOperationAction(ISD::SIGN_EXTEND,        MVT::v16i32, Custom);  in X86TargetLowering()
1449     setOperationAction(ISD::SIGN_EXTEND,        MVT::v8i64, Custom);  in X86TargetLowering()
1450     setOperationAction(ISD::SIGN_EXTEND,        MVT::v16i8, Custom);  in X86TargetLowering()
1451     setOperationAction(ISD::SIGN_EXTEND,        MVT::v8i16, Custom);  in X86TargetLowering()
1452     setOperationAction(ISD::SIGN_EXTEND,        MVT::v16i16, Custom);  in X86TargetLowering()
1454       setOperationAction(ISD::SIGN_EXTEND,        MVT::v4i32, Custom);  in X86TargetLowering()
1455       setOperationAction(ISD::SIGN_EXTEND,        MVT::v2i64, Custom);  in X86TargetLowering()
1648     setOperationAction(ISD::SIGN_EXTEND,        MVT::v32i8, Custom);  in X86TargetLowering()
1650     setOperationAction(ISD::SIGN_EXTEND,        MVT::v32i16, Custom);  in X86TargetLowering()
1654     setOperationAction(ISD::SIGN_EXTEND,        MVT::v64i8, Custom);  in X86TargetLowering()
1818   setTargetDAGCombine(ISD::SIGN_EXTEND);  in X86TargetLowering()
2221       ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);  in LowerReturn()
2226         ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);  in LowerReturn()
3196       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);  in LowerCall()
3204         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);  in LowerCall()
11218     V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);  in lower1BitVectorShuffle()
11227     V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);  in lower1BitVectorShuffle()
12527                          DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));  in LowerSINT_TO_FP()
13302       In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);  in LowerTRUNCATE()
14013           isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;  in EmitCmp()
16588       return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);  in LowerINTRINSIC_WO_CHAIN()
18014                       DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),  in LowerMUL()
18015                       DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));  in LowerMUL()
18894         Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in LowerShift()
19854       Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);  in LowerMSCATTER()
19863         Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);  in LowerMSCATTER()
19969       Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);  in LowerMGATHER()
19982       Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);  in LowerMGATHER()
20083   case ISD::SIGN_EXTEND:        return LowerSIGN_EXTEND(Op, Subtarget, DAG);  in LowerOperation()
23834     if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&  in PerformEXTRACT_VECTOR_ELTCombine()
23922   if (Cond.getOpcode() == ISD::SIGN_EXTEND) {  in transformVSELECTtoBlendVECTOR_SHUFFLE()
24130       Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);  in PerformSELECTCombine()
24978     } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&  in PerformSHLCombine()
25151         case ISD::SIGN_EXTEND:  in CMPEQCombine()
25259           N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");  in WidenMaskArithmetic()
25321   case ISD::SIGN_EXTEND:  in WidenMaskArithmetic()
26938       N0.getOpcode() == ISD::SIGN_EXTEND)) {  in PerformSIGN_EXTEND_INREGCombine()
26950       return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);  in PerformSIGN_EXTEND_INREGCombine()
26997   SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);  in promoteSextBeforeAddNSW()
27060       SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);  in PerformSExtCombine()
27232         (LHS.getOpcode() == ISD::SIGN_EXTEND) &&  in PerformISDSETCCCombine()
27241       IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&  in PerformISDSETCCCombine()
27473     SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);  in PerformSINT_TO_FPCombine()
27723   case ISD::SIGN_EXTEND:    return PerformSExtCombine(N, DAG, DCI, Subtarget);  in PerformDAGCombine()
27768   case ISD::SIGN_EXTEND:  in isTypeDesirableForOp()
27812   case ISD::SIGN_EXTEND:  in IsDesirableToPromoteOp()