1315     addRegisterClass(MVT::v8i1,   &X86::VK8RegClass);  in X86TargetLowering()
1372     setOperationAction(ISD::SINT_TO_FP,         MVT::v8i1,   Custom);  in X86TargetLowering()
1410     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8i1,  Custom);  in X86TargetLowering()
1441     setOperationAction(ISD::TRUNCATE,           MVT::v8i1, Custom);  in X86TargetLowering()
1475     setOperationAction(ISD::SETCC,              MVT::v8i1, Custom);  in X86TargetLowering()
1479     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1,  Custom);  in X86TargetLowering()
1483     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i1, Custom);  in X86TargetLowering()
1484     setOperationAction(ISD::BUILD_VECTOR,       MVT::v8i1, Custom);  in X86TargetLowering()
1490     setOperationAction(ISD::SELECT,             MVT::v8i1,  Custom);  in X86TargetLowering()
1709     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v8i1, Custom);  in X86TargetLowering()
1710     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v8i1, Custom);  in X86TargetLowering()
1877           case  8: return MVT::v8i1;  in getSetCCResultType()
1895           case 8: return MVT::v8i1;  in getSetCCResultType()
1900           case  8: return MVT::v8i1;  in getSetCCResultType()
2722       else if (RegVT == MVT::v8i1)  in LowerFormalArguments()
5803     SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);  in LowerBUILD_VECTORvXi1()
5850     SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);  in LowerBUILD_VECTORvXi1()
11199   case MVT::v8i1:  in lower1BitVectorShuffle()
11562     MVT ExtVT = (VecVT == MVT::v8i1 ?  MVT::v8i64 : MVT::v16i32);  in ExtractBitFromMaskVector()
11706     MVT ExtVecVT = (VecVT == MVT::v8i1 ?  MVT::v8i64 : MVT::v16i32);  in InsertBitToMaskVector()
11707     MVT ExtEltVT = (VecVT == MVT::v8i1 ?  MVT::i64 : MVT::i32);  in InsertBitToMaskVector()
14891       SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);  in LowerSELECT()
14899     Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,  in LowerSELECT()
14900                       DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);  in LowerSELECT()
14901     Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,  in LowerSELECT()
14902                       DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);  in LowerSELECT()
14903     SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,  in LowerSELECT()
19899       !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {  in LowerMLOAD()
19931       !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {  in LowerMSTORE()