Lines Matching refs:XD
608 SSEPackedDouble>, XD;
616 SSEPackedDouble>, XD;
1518 XD, VEX, VEX_LIG;
1522 XD, VEX, VEX_W, VEX_LIG;
1550 XD, VEX_4V, VEX_LIG;
1552 XD, VEX_4V, VEX_W, VEX_LIG;
1587 SSE_CVT_SD2SI>, XD;
1590 SSE_CVT_SD2SI>, XD, REX_W;
1599 SSE_CVT_Scalar>, XD;
1602 SSE_CVT_Scalar>, XD, REX_W;
1664 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1667 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1670 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1672 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1686 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1689 SSE_CVT_Scalar, 0>, XD,
1701 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1704 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1722 SSE_CVT_SD2SI>, XD, VEX;
1726 XD, VEX, VEX_W;
1736 SSE_CVT_SD2SI>, XD;
1739 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1821 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1836 XD,
1845 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1852 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1861 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1868 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
2375 XD, VEX_4V, VEX_LIG;
2385 SSE_ALU_F64S, i8immZExt3>, XD;
2414 XD, VEX_4V;
2422 XD;
3077 XD, VEX_4V, VEX_LIG;
3085 itins.d>, XD;
3096 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3104 SSEPackedDouble, itins.d>, XD;
3536 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3541 XD, VEX_4V, VEX_LIG;
4322 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
5277 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5279 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5291 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
7778 imm:$len, imm:$idx))]>, XD;
7783 VR128:$mask))]>, XD;
7792 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;