Lines Matching refs:src3

150            (ins VR128:$src1, VR128:$src2, VR128:$src3),
152            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
154               (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
156            (ins VR128:$src1, i128mem:$src2, VR128:$src3),
158            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
161               VR128:$src3))]>, XOP_4V, VEX_I8IMM;
201                  (ins VR128:$src1, VR128:$src2, u8imm:$src3),
203                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
207                  (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
209                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
228            (ins VR128:$src1, VR128:$src2, VR128:$src3),
230            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
231            [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
234            (ins VR128:$src1, VR128:$src2, i128mem:$src3),
236            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
239               (bitconvert (loadv2i64 addr:$src3))))]>,
242            (ins VR128:$src1, i128mem:$src2, VR128:$src3),
244            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
247               VR128:$src3))]>,
258            (ins VR256:$src1, VR256:$src2, VR256:$src3),
260            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
261            [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
264            (ins VR256:$src1, VR256:$src2, i256mem:$src3),
266            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
269               (bitconvert (loadv4i64 addr:$src3))))]>,
272            (ins VR256:$src1, f256mem:$src2, VR256:$src3),
274            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
277               VR256:$src3))]>,
285   def : Pat<(v2i64 (or (and VR128:$src3, VR128:$src1),
286                        (X86andnp VR128:$src3, VR128:$src2))),
287             (VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
289   def : Pat<(v4i64 (or (and VR256:$src3, VR256:$src1),
290                        (X86andnp VR256:$src3, VR256:$src2))),
291             (VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
297         (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4),
299         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
301            (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
303         (ins VR128:$src1, VR128:$src2, f128mem:$src3, u8imm:$src4),
305         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
307            (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
310         (ins VR128:$src1, f128mem:$src2, VR128:$src3, u8imm:$src4),
312         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
314            (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
316         (ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
318         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
320           (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
322         (ins VR256:$src1, VR256:$src2, f256mem:$src3, u8imm:$src4),
324         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
326           (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
329         (ins VR256:$src1, f256mem:$src2, VR256:$src3, u8imm:$src4),
331         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
333            (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,