Lines Matching refs:td

4 define transform-td-to-out
6 	$(call transform-host-td-to-out,$(1)),	\
7 	$(call transform-device-td-to-out,$(1)))
32 tblgen_td_deps := $(tblgen_source_dir)/../*.td
34 tblgen_td_deps := $(tblgen_source_dir)/*.td
43 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
45 	$(call transform-td-to-out, register-info)
48 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
50 	$(call transform-td-to-out,instr-info)
53 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
55 	$(call transform-td-to-out,subtarget)
60 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
62 	$(call transform-td-to-out, register-info)
65 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
67 	$(call transform-td-to-out,instr-info)
70 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
72 	$(call transform-td-to-out,subtarget)
77 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
79 	$(call transform-td-to-out, register-info)
82 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
84 	$(call transform-td-to-out,instr-info)
87 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
89 	$(call transform-td-to-out,subtarget)
95 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
97 	$(call transform-td-to-out,register-info)
102 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
104 	$(call transform-td-to-out,instr-info)
109 $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
111 	$(call transform-td-to-out,asm-writer)
116 $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
118 	$(call transform-td-to-out,asm-writer -asmwriternum=1)
123 $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
125 	$(call transform-td-to-out,asm-matcher)
131 $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
133 	$(call transform-td-to-out,emitter)
138 $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
140 	$(call transform-td-to-out,emitter)
145 $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
147 	$(call transform-td-to-out,pseudo-lowering)
152 $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
154 	$(call transform-td-to-out,dag-isel)
159 $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
161 	$(call transform-td-to-out,disassembler)
166 $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
168 	$(call transform-td-to-out,enhanced-disassembly-info)
173 $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
175 	$(call transform-td-to-out,fast-isel)
180 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
182 	$(call transform-td-to-out,subtarget)
187 $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
189 	$(call transform-td-to-out,callingconv)
194 $(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
196 	$(call transform-td-to-out,tgt_intrinsics)
201 $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
203 	$(call transform-td-to-out,arm-decoder)
208 $(generated_sources)/Options.inc: $(tblgen_source_dir)/Options.td \
211                                      $(LLVM_ROOT_PATH)/include/llvm/Option/OptParser.td
212 	$(call transform-td-to-out,opt-parser-defs)