Lines Matching refs:rd
1079 void Assembler::adr(const Register& rd, int imm21) { in adr() argument
1080 DCHECK(rd.Is64Bits()); in adr()
1081 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
1085 void Assembler::adr(const Register& rd, Label* label) { in adr() argument
1086 adr(rd, LinkAndGetByteOffsetTo(label)); in adr()
1090 void Assembler::add(const Register& rd, in add() argument
1093 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
1097 void Assembler::adds(const Register& rd, in adds() argument
1100 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
1111 void Assembler::sub(const Register& rd, in sub() argument
1114 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
1118 void Assembler::subs(const Register& rd, in subs() argument
1121 AddSub(rd, rn, operand, SetFlags, SUB); in subs()
1131 void Assembler::neg(const Register& rd, const Operand& operand) { in neg() argument
1132 Register zr = AppropriateZeroRegFor(rd); in neg()
1133 sub(rd, zr, operand); in neg()
1137 void Assembler::negs(const Register& rd, const Operand& operand) { in negs() argument
1138 Register zr = AppropriateZeroRegFor(rd); in negs()
1139 subs(rd, zr, operand); in negs()
1143 void Assembler::adc(const Register& rd, in adc() argument
1146 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC); in adc()
1150 void Assembler::adcs(const Register& rd, in adcs() argument
1153 AddSubWithCarry(rd, rn, operand, SetFlags, ADC); in adcs()
1157 void Assembler::sbc(const Register& rd, in sbc() argument
1160 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC); in sbc()
1164 void Assembler::sbcs(const Register& rd, in sbcs() argument
1167 AddSubWithCarry(rd, rn, operand, SetFlags, SBC); in sbcs()
1171 void Assembler::ngc(const Register& rd, const Operand& operand) { in ngc() argument
1172 Register zr = AppropriateZeroRegFor(rd); in ngc()
1173 sbc(rd, zr, operand); in ngc()
1177 void Assembler::ngcs(const Register& rd, const Operand& operand) { in ngcs() argument
1178 Register zr = AppropriateZeroRegFor(rd); in ngcs()
1179 sbcs(rd, zr, operand); in ngcs()
1184 void Assembler::and_(const Register& rd, in and_() argument
1187 Logical(rd, rn, operand, AND); in and_()
1191 void Assembler::ands(const Register& rd, in ands() argument
1194 Logical(rd, rn, operand, ANDS); in ands()
1204 void Assembler::bic(const Register& rd, in bic() argument
1207 Logical(rd, rn, operand, BIC); in bic()
1211 void Assembler::bics(const Register& rd, in bics() argument
1214 Logical(rd, rn, operand, BICS); in bics()
1218 void Assembler::orr(const Register& rd, in orr() argument
1221 Logical(rd, rn, operand, ORR); in orr()
1225 void Assembler::orn(const Register& rd, in orn() argument
1228 Logical(rd, rn, operand, ORN); in orn()
1232 void Assembler::eor(const Register& rd, in eor() argument
1235 Logical(rd, rn, operand, EOR); in eor()
1239 void Assembler::eon(const Register& rd, in eon() argument
1242 Logical(rd, rn, operand, EON); in eon()
1246 void Assembler::lslv(const Register& rd, in lslv() argument
1249 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in lslv()
1250 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in lslv()
1251 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1255 void Assembler::lsrv(const Register& rd, in lsrv() argument
1258 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in lsrv()
1259 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in lsrv()
1260 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1264 void Assembler::asrv(const Register& rd, in asrv() argument
1267 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in asrv()
1268 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in asrv()
1269 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1273 void Assembler::rorv(const Register& rd, in rorv() argument
1276 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in rorv()
1277 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in rorv()
1278 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1283 void Assembler::bfm(const Register& rd, const Register& rn, int immr, in bfm() argument
1285 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in bfm()
1286 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in bfm()
1287 Emit(SF(rd) | BFM | N | in bfm()
1288 ImmR(immr, rd.SizeInBits()) | in bfm()
1290 Rn(rn) | Rd(rd)); in bfm()
1294 void Assembler::sbfm(const Register& rd, const Register& rn, int immr, in sbfm() argument
1296 DCHECK(rd.Is64Bits() || rn.Is32Bits()); in sbfm()
1297 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in sbfm()
1298 Emit(SF(rd) | SBFM | N | in sbfm()
1299 ImmR(immr, rd.SizeInBits()) | in sbfm()
1301 Rn(rn) | Rd(rd)); in sbfm()
1305 void Assembler::ubfm(const Register& rd, const Register& rn, int immr, in ubfm() argument
1307 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in ubfm()
1308 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in ubfm()
1309 Emit(SF(rd) | UBFM | N | in ubfm()
1310 ImmR(immr, rd.SizeInBits()) | in ubfm()
1312 Rn(rn) | Rd(rd)); in ubfm()
1316 void Assembler::extr(const Register& rd, const Register& rn, const Register& rm, in extr() argument
1318 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in extr()
1319 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in extr()
1320 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in extr()
1321 Emit(SF(rd) | EXTR | N | Rm(rm) | in extr()
1322 ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in extr()
1326 void Assembler::csel(const Register& rd, in csel() argument
1330 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
1334 void Assembler::csinc(const Register& rd, in csinc() argument
1338 ConditionalSelect(rd, rn, rm, cond, CSINC); in csinc()
1342 void Assembler::csinv(const Register& rd, in csinv() argument
1346 ConditionalSelect(rd, rn, rm, cond, CSINV); in csinv()
1350 void Assembler::csneg(const Register& rd, in csneg() argument
1354 ConditionalSelect(rd, rn, rm, cond, CSNEG); in csneg()
1358 void Assembler::cset(const Register &rd, Condition cond) { in cset() argument
1360 Register zr = AppropriateZeroRegFor(rd); in cset()
1361 csinc(rd, zr, zr, NegateCondition(cond)); in cset()
1365 void Assembler::csetm(const Register &rd, Condition cond) { in csetm() argument
1367 Register zr = AppropriateZeroRegFor(rd); in csetm()
1368 csinv(rd, zr, zr, NegateCondition(cond)); in csetm()
1372 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) { in cinc() argument
1374 csinc(rd, rn, rn, NegateCondition(cond)); in cinc()
1378 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) { in cinv() argument
1380 csinv(rd, rn, rn, NegateCondition(cond)); in cinv()
1384 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) { in cneg() argument
1386 csneg(rd, rn, rn, NegateCondition(cond)); in cneg()
1390 void Assembler::ConditionalSelect(const Register& rd, in ConditionalSelect() argument
1395 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in ConditionalSelect()
1396 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in ConditionalSelect()
1397 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
1417 void Assembler::DataProcessing3Source(const Register& rd, in DataProcessing3Source() argument
1422 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
1426 void Assembler::mul(const Register& rd, in mul() argument
1429 DCHECK(AreSameSizeAndType(rd, rn, rm)); in mul()
1431 DataProcessing3Source(rd, rn, rm, zr, MADD); in mul()
1435 void Assembler::madd(const Register& rd, in madd() argument
1439 DCHECK(AreSameSizeAndType(rd, rn, rm, ra)); in madd()
1440 DataProcessing3Source(rd, rn, rm, ra, MADD); in madd()
1444 void Assembler::mneg(const Register& rd, in mneg() argument
1447 DCHECK(AreSameSizeAndType(rd, rn, rm)); in mneg()
1449 DataProcessing3Source(rd, rn, rm, zr, MSUB); in mneg()
1453 void Assembler::msub(const Register& rd, in msub() argument
1457 DCHECK(AreSameSizeAndType(rd, rn, rm, ra)); in msub()
1458 DataProcessing3Source(rd, rn, rm, ra, MSUB); in msub()
1462 void Assembler::smaddl(const Register& rd, in smaddl() argument
1466 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in smaddl()
1468 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x); in smaddl()
1472 void Assembler::smsubl(const Register& rd, in smsubl() argument
1476 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in smsubl()
1478 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x); in smsubl()
1482 void Assembler::umaddl(const Register& rd, in umaddl() argument
1486 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in umaddl()
1488 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x); in umaddl()
1492 void Assembler::umsubl(const Register& rd, in umsubl() argument
1496 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in umsubl()
1498 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x); in umsubl()
1502 void Assembler::smull(const Register& rd, in smull() argument
1505 DCHECK(rd.Is64Bits()); in smull()
1507 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x); in smull()
1511 void Assembler::smulh(const Register& rd, in smulh() argument
1514 DCHECK(AreSameSizeAndType(rd, rn, rm)); in smulh()
1515 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x); in smulh()
1519 void Assembler::sdiv(const Register& rd, in sdiv() argument
1522 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in sdiv()
1523 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in sdiv()
1524 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd)); in sdiv()
1528 void Assembler::udiv(const Register& rd, in udiv() argument
1531 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in udiv()
1532 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in udiv()
1533 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd)); in udiv()
1537 void Assembler::rbit(const Register& rd, in rbit() argument
1539 DataProcessing1Source(rd, rn, RBIT); in rbit()
1543 void Assembler::rev16(const Register& rd, in rev16() argument
1545 DataProcessing1Source(rd, rn, REV16); in rev16()
1549 void Assembler::rev32(const Register& rd, in rev32() argument
1551 DCHECK(rd.Is64Bits()); in rev32()
1552 DataProcessing1Source(rd, rn, REV); in rev32()
1556 void Assembler::rev(const Register& rd, in rev() argument
1558 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w); in rev()
1562 void Assembler::clz(const Register& rd, in clz() argument
1564 DataProcessing1Source(rd, rn, CLZ); in clz()
1568 void Assembler::cls(const Register& rd, in cls() argument
1570 DataProcessing1Source(rd, rn, CLS); in cls()
1772 void Assembler::mov(const Register& rd, const Register& rm) { in mov() argument
1776 if (rd.IsSP() || rm.IsSP()) { in mov()
1777 add(rd, rm, 0); in mov()
1779 orr(rd, AppropriateZeroRegFor(rd), rm); in mov()
1784 void Assembler::mvn(const Register& rd, const Operand& operand) { in mvn() argument
1785 orn(rd, AppropriateZeroRegFor(rd), operand); in mvn()
1835 void Assembler::fmov(Register rd, FPRegister fn) { in fmov() argument
1836 DCHECK(rd.SizeInBits() == fn.SizeInBits()); in fmov()
1837 FPIntegerConvertOp op = rd.Is32Bits() ? FMOV_ws : FMOV_xd; in fmov()
1838 Emit(op | Rd(rd) | Rn(fn)); in fmov()
2035 void Assembler::FPConvertToInt(const Register& rd, in FPConvertToInt() argument
2038 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd)); in FPConvertToInt()
2056 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() argument
2057 FPConvertToInt(rd, fn, FCVTAU); in fcvtau()
2061 void Assembler::fcvtas(const Register& rd, const FPRegister& fn) { in fcvtas() argument
2062 FPConvertToInt(rd, fn, FCVTAS); in fcvtas()
2066 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) { in fcvtmu() argument
2067 FPConvertToInt(rd, fn, FCVTMU); in fcvtmu()
2071 void Assembler::fcvtms(const Register& rd, const FPRegister& fn) { in fcvtms() argument
2072 FPConvertToInt(rd, fn, FCVTMS); in fcvtms()
2076 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) { in fcvtnu() argument
2077 FPConvertToInt(rd, fn, FCVTNU); in fcvtnu()
2081 void Assembler::fcvtns(const Register& rd, const FPRegister& fn) { in fcvtns() argument
2082 FPConvertToInt(rd, fn, FCVTNS); in fcvtns()
2086 void Assembler::fcvtzu(const Register& rd, const FPRegister& fn) { in fcvtzu() argument
2087 FPConvertToInt(rd, fn, FCVTZU); in fcvtzu()
2091 void Assembler::fcvtzs(const Register& rd, const FPRegister& fn) { in fcvtzs() argument
2092 FPConvertToInt(rd, fn, FCVTZS); in fcvtzs()
2200 void Assembler::MoveWide(const Register& rd, in MoveWide() argument
2205 if (rd.Is32Bits()) { in MoveWide()
2216 DCHECK(rd.Is64Bits() || (shift == 0) || (shift == 16)); in MoveWide()
2228 DCHECK(rd.Is64Bits()); in MoveWide()
2232 DCHECK(rd.Is64Bits()); in MoveWide()
2240 Emit(SF(rd) | MoveWideImmediateFixed | mov_op | Rd(rd) | in MoveWide()
2245 void Assembler::AddSub(const Register& rd, in AddSub() argument
2250 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in AddSub()
2255 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd); in AddSub()
2256 Emit(SF(rd) | AddSubImmediateFixed | op | Flags(S) | in AddSub()
2259 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits()); in AddSub()
2269 if (rn.IsSP() || rd.IsSP()) { in AddSub()
2270 DCHECK(!(rd.IsSP() && (S == SetFlags))); in AddSub()
2271 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S, in AddSub()
2274 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op); in AddSub()
2278 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op); in AddSub()
2283 void Assembler::AddSubWithCarry(const Register& rd, in AddSubWithCarry() argument
2288 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in AddSubWithCarry()
2289 DCHECK(rd.SizeInBits() == operand.reg().SizeInBits()); in AddSubWithCarry()
2292 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd)); in AddSubWithCarry()
2353 void Assembler::Logical(const Register& rd, in Logical() argument
2357 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in Logical()
2361 unsigned reg_size = rd.SizeInBits(); in Logical()
2365 DCHECK(rd.Is64Bits() || is_uint32(immediate)); in Logical()
2370 immediate = rd.Is64Bits() ? ~immediate : (~immediate & kWRegMask); in Logical()
2376 LogicalImmediate(rd, rn, n, imm_s, imm_r, op); in Logical()
2383 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits()); in Logical()
2385 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op); in Logical()
2390 void Assembler::LogicalImmediate(const Register& rd, in LogicalImmediate() argument
2396 unsigned reg_size = rd.SizeInBits(); in LogicalImmediate()
2397 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
2398 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) | in LogicalImmediate()
2424 void Assembler::DataProcessing1Source(const Register& rd, in DataProcessing1Source() argument
2427 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in DataProcessing1Source()
2428 Emit(SF(rn) | op | Rn(rn) | Rd(rd)); in DataProcessing1Source()
2459 void Assembler::EmitShift(const Register& rd, in EmitShift() argument
2465 lsl(rd, rn, shift_amount); in EmitShift()
2468 lsr(rd, rn, shift_amount); in EmitShift()
2471 asr(rd, rn, shift_amount); in EmitShift()
2474 ror(rd, rn, shift_amount); in EmitShift()
2482 void Assembler::EmitExtendShift(const Register& rd, in EmitExtendShift() argument
2486 DCHECK(rd.SizeInBits() >= rn.SizeInBits()); in EmitExtendShift()
2487 unsigned reg_size = rd.SizeInBits(); in EmitExtendShift()
2489 Register rn_ = Register::Create(rn.code(), rd.SizeInBits()); in EmitExtendShift()
2499 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
2502 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
2507 lsl(rd, rn_, left_shift); in EmitExtendShift()
2514 lsl(rd, rn_, left_shift); in EmitExtendShift()
2519 void Assembler::DataProcShiftedRegister(const Register& rd, in DataProcShiftedRegister() argument
2527 Emit(SF(rd) | op | Flags(S) | in DataProcShiftedRegister()
2529 Rm(operand.reg()) | Rn(rn) | Rd(rd)); in DataProcShiftedRegister()
2533 void Assembler::DataProcExtendedRegister(const Register& rd, in DataProcExtendedRegister() argument
2539 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd); in DataProcExtendedRegister()
2540 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | in DataProcExtendedRegister()
3209 Register rd = Register::XRegFromCode(rd_code); in PatchAdrFar() local
3212 adr(rd, target_offset & 0xFFFF); in PatchAdrFar()
3216 add(rd, rd, scratch); in PatchAdrFar()