Lines Matching refs:opnd
3786 void MacroAssembler::MulP(Register dst, const Operand& opnd) { in MulP() argument
3788 msgfi(dst, opnd); in MulP()
3790 msfi(dst, opnd); in MulP()
3802 void MacroAssembler::MulP(Register dst, const MemOperand& opnd) { in MulP() argument
3804 if (is_uint16(opnd.offset())) { in MulP()
3805 ms(dst, opnd); in MulP()
3806 } else if (is_int20(opnd.offset())) { in MulP()
3807 msy(dst, opnd); in MulP()
3812 if (is_int20(opnd.offset())) { in MulP()
3813 msg(dst, opnd); in MulP()
3825 void MacroAssembler::Add32(Register dst, const Operand& opnd) { in Add32() argument
3826 if (is_int16(opnd.immediate())) in Add32()
3827 ahi(dst, opnd); in Add32()
3829 afi(dst, opnd); in Add32()
3833 void MacroAssembler::AddP(Register dst, const Operand& opnd) { in AddP() argument
3835 if (is_int16(opnd.immediate())) in AddP()
3836 aghi(dst, opnd); in AddP()
3838 agfi(dst, opnd); in AddP()
3840 Add32(dst, opnd); in AddP()
3845 void MacroAssembler::Add32(Register dst, Register src, const Operand& opnd) { in Add32() argument
3847 if (CpuFeatures::IsSupported(DISTINCT_OPS) && is_int16(opnd.immediate())) { in Add32()
3848 ahik(dst, src, opnd); in Add32()
3853 Add32(dst, opnd); in Add32()
3857 void MacroAssembler::AddP(Register dst, Register src, const Operand& opnd) { in AddP() argument
3859 if (CpuFeatures::IsSupported(DISTINCT_OPS) && is_int16(opnd.immediate())) { in AddP()
3860 AddPImm_RRI(dst, src, opnd); in AddP()
3865 AddP(dst, opnd); in AddP()
3942 void MacroAssembler::Add32(Register dst, const MemOperand& opnd) { in Add32() argument
3943 DCHECK(is_int20(opnd.offset())); in Add32()
3944 if (is_uint12(opnd.offset())) in Add32()
3945 a(dst, opnd); in Add32()
3947 ay(dst, opnd); in Add32()
3951 void MacroAssembler::AddP(Register dst, const MemOperand& opnd) { in AddP() argument
3953 DCHECK(is_int20(opnd.offset())); in AddP()
3954 ag(dst, opnd); in AddP()
3956 Add32(dst, opnd); in AddP()
3964 void MacroAssembler::AddP_ExtendSrc(Register dst, const MemOperand& opnd) { in AddP_ExtendSrc() argument
3966 DCHECK(is_int20(opnd.offset())); in AddP_ExtendSrc()
3967 agf(dst, opnd); in AddP_ExtendSrc()
3969 Add32(dst, opnd); in AddP_ExtendSrc()
3974 void MacroAssembler::Add32(const MemOperand& opnd, const Operand& imm) { in Add32() argument
3976 DCHECK(is_int20(opnd.offset())); in Add32()
3978 asi(opnd, imm); in Add32()
3982 void MacroAssembler::AddP(const MemOperand& opnd, const Operand& imm) { in AddP() argument
3984 DCHECK(is_int20(opnd.offset())); in AddP()
3987 agsi(opnd, imm); in AddP()
3989 asi(opnd, imm); in AddP()
4045 void MacroAssembler::AddLogical(Register dst, const MemOperand& opnd) { in AddLogical() argument
4046 DCHECK(is_int20(opnd.offset())); in AddLogical()
4047 if (is_uint12(opnd.offset())) in AddLogical()
4048 al_z(dst, opnd); in AddLogical()
4050 aly(dst, opnd); in AddLogical()
4054 void MacroAssembler::AddLogicalP(Register dst, const MemOperand& opnd) { in AddLogicalP() argument
4056 DCHECK(is_int20(opnd.offset())); in AddLogicalP()
4057 alg(dst, opnd); in AddLogicalP()
4059 AddLogical(dst, opnd); in AddLogicalP()
4198 void MacroAssembler::Sub32(Register dst, const MemOperand& opnd) { in Sub32() argument
4199 DCHECK(is_int20(opnd.offset())); in Sub32()
4200 if (is_uint12(opnd.offset())) in Sub32()
4201 s(dst, opnd); in Sub32()
4203 sy(dst, opnd); in Sub32()
4207 void MacroAssembler::SubP(Register dst, const MemOperand& opnd) { in SubP() argument
4209 sg(dst, opnd); in SubP()
4211 Sub32(dst, opnd); in SubP()
4225 void MacroAssembler::SubP_ExtendSrc(Register dst, const MemOperand& opnd) { in SubP_ExtendSrc() argument
4227 DCHECK(is_int20(opnd.offset())); in SubP_ExtendSrc()
4228 sgf(dst, opnd); in SubP_ExtendSrc()
4230 Sub32(dst, opnd); in SubP_ExtendSrc()
4239 void MacroAssembler::SubLogical(Register dst, const MemOperand& opnd) { in SubLogical() argument
4240 DCHECK(is_int20(opnd.offset())); in SubLogical()
4241 if (is_uint12(opnd.offset())) in SubLogical()
4242 sl(dst, opnd); in SubLogical()
4244 sly(dst, opnd); in SubLogical()
4248 void MacroAssembler::SubLogicalP(Register dst, const MemOperand& opnd) { in SubLogicalP() argument
4249 DCHECK(is_int20(opnd.offset())); in SubLogicalP()
4251 slgf(dst, opnd); in SubLogicalP()
4253 SubLogical(dst, opnd); in SubLogicalP()
4262 const MemOperand& opnd) { in SubLogicalP_ExtendSrc() argument
4264 DCHECK(is_int20(opnd.offset())); in SubLogicalP_ExtendSrc()
4265 slgf(dst, opnd); in SubLogicalP_ExtendSrc()
4267 SubLogical(dst, opnd); in SubLogicalP_ExtendSrc()
4316 void MacroAssembler::And(Register dst, const MemOperand& opnd) { in And() argument
4317 DCHECK(is_int20(opnd.offset())); in And()
4318 if (is_uint12(opnd.offset())) in And()
4319 n(dst, opnd); in And()
4321 ny(dst, opnd); in And()
4325 void MacroAssembler::AndP(Register dst, const MemOperand& opnd) { in AndP() argument
4326 DCHECK(is_int20(opnd.offset())); in AndP()
4328 ng(dst, opnd); in AndP()
4330 And(dst, opnd); in AndP()
4335 void MacroAssembler::And(Register dst, const Operand& opnd) { nilf(dst, opnd); } in And() argument
4338 void MacroAssembler::AndP(Register dst, const Operand& opnd) { in AndP() argument
4340 intptr_t value = opnd.imm_; in AndP()
4347 And(dst, opnd); in AndP()
4352 void MacroAssembler::And(Register dst, Register src, const Operand& opnd) { in And() argument
4354 nilf(dst, opnd); in And()
4358 void MacroAssembler::AndP(Register dst, Register src, const Operand& opnd) { in AndP() argument
4360 intptr_t value = opnd.imm_; in AndP()
4394 AndP(dst, opnd); in AndP()
4438 void MacroAssembler::Or(Register dst, const MemOperand& opnd) { in Or() argument
4439 DCHECK(is_int20(opnd.offset())); in Or()
4440 if (is_uint12(opnd.offset())) in Or()
4441 o(dst, opnd); in Or()
4443 oy(dst, opnd); in Or()
4447 void MacroAssembler::OrP(Register dst, const MemOperand& opnd) { in OrP() argument
4448 DCHECK(is_int20(opnd.offset())); in OrP()
4450 og(dst, opnd); in OrP()
4452 Or(dst, opnd); in OrP()
4457 void MacroAssembler::Or(Register dst, const Operand& opnd) { oilf(dst, opnd); } in Or() argument
4460 void MacroAssembler::OrP(Register dst, const Operand& opnd) { in OrP() argument
4462 intptr_t value = opnd.imm_; in OrP()
4469 Or(dst, opnd); in OrP()
4474 void MacroAssembler::Or(Register dst, Register src, const Operand& opnd) { in Or() argument
4476 oilf(dst, opnd); in Or()
4480 void MacroAssembler::OrP(Register dst, Register src, const Operand& opnd) { in OrP() argument
4482 OrP(dst, opnd); in OrP()
4526 void MacroAssembler::Xor(Register dst, const MemOperand& opnd) { in Xor() argument
4527 DCHECK(is_int20(opnd.offset())); in Xor()
4528 if (is_uint12(opnd.offset())) in Xor()
4529 x(dst, opnd); in Xor()
4531 xy(dst, opnd); in Xor()
4535 void MacroAssembler::XorP(Register dst, const MemOperand& opnd) { in XorP() argument
4536 DCHECK(is_int20(opnd.offset())); in XorP()
4538 xg(dst, opnd); in XorP()
4540 Xor(dst, opnd); in XorP()
4545 void MacroAssembler::Xor(Register dst, const Operand& opnd) { xilf(dst, opnd); } in Xor() argument
4548 void MacroAssembler::XorP(Register dst, const Operand& opnd) { in XorP() argument
4550 intptr_t value = opnd.imm_; in XorP()
4554 Xor(dst, opnd); in XorP()
4559 void MacroAssembler::Xor(Register dst, Register src, const Operand& opnd) { in Xor() argument
4561 xilf(dst, opnd); in Xor()
4565 void MacroAssembler::XorP(Register dst, Register src, const Operand& opnd) { in XorP() argument
4567 XorP(dst, opnd); in XorP()
4580 void MacroAssembler::Load(Register dst, const Operand& opnd) { in Load() argument
4581 intptr_t value = opnd.immediate(); in Load()
4584 lghi(dst, opnd); in Load()
4586 lhi(dst, opnd); in Load()
4590 llilf(dst, opnd); in Load()
4592 iilf(dst, opnd); in Load()
4597 void MacroAssembler::Load(Register dst, const MemOperand& opnd) { in Load() argument
4598 DCHECK(is_int20(opnd.offset())); in Load()
4600 lgf(dst, opnd); // 64<-32 in Load()
4602 if (is_uint12(opnd.offset())) { in Load()
4603 l(dst, opnd); in Load()
4605 ly(dst, opnd); in Load()
4628 void MacroAssembler::Cmp32(Register dst, const Operand& opnd) { in Cmp32() argument
4629 if (opnd.rmode_ == kRelocInfo_NONEPTR) { in Cmp32()
4630 intptr_t value = opnd.immediate(); in Cmp32()
4632 chi(dst, opnd); in Cmp32()
4634 cfi(dst, opnd); in Cmp32()
4637 RecordRelocInfo(opnd.rmode_, opnd.imm_); in Cmp32()
4638 cfi(dst, opnd); in Cmp32()
4644 void MacroAssembler::CmpP(Register dst, const Operand& opnd) { in CmpP() argument
4646 if (opnd.rmode_ == kRelocInfo_NONEPTR) { in CmpP()
4647 cgfi(dst, opnd); in CmpP()
4649 mov(r0, opnd); // Need to generate 64-bit relocation in CmpP()
4653 Cmp32(dst, opnd); in CmpP()
4658 void MacroAssembler::Cmp32(Register dst, const MemOperand& opnd) { in Cmp32() argument
4660 DCHECK(is_int20(opnd.offset())); in Cmp32()
4661 if (is_uint12(opnd.offset())) in Cmp32()
4662 c(dst, opnd); in Cmp32()
4664 cy(dst, opnd); in Cmp32()
4668 void MacroAssembler::CmpP(Register dst, const MemOperand& opnd) { in CmpP() argument
4670 DCHECK(is_int20(opnd.offset())); in CmpP()
4672 cg(dst, opnd); in CmpP()
4674 Cmp32(dst, opnd); in CmpP()
4695 void MacroAssembler::CmpLogical32(Register dst, const Operand& opnd) { in CmpLogical32() argument
4696 clfi(dst, opnd); in CmpLogical32()
4700 void MacroAssembler::CmpLogicalP(Register dst, const Operand& opnd) { in CmpLogicalP() argument
4702 DCHECK(static_cast<uint32_t>(opnd.immediate() >> 32) == 0); in CmpLogicalP()
4703 clgfi(dst, opnd); in CmpLogicalP()
4705 CmpLogical32(dst, opnd); in CmpLogicalP()
4710 void MacroAssembler::CmpLogical32(Register dst, const MemOperand& opnd) { in CmpLogical32() argument
4712 DCHECK(is_int20(opnd.offset())); in CmpLogical32()
4713 if (is_uint12(opnd.offset())) in CmpLogical32()
4714 cl(dst, opnd); in CmpLogical32()
4716 cly(dst, opnd); in CmpLogical32()
4720 void MacroAssembler::CmpLogicalP(Register dst, const MemOperand& opnd) { in CmpLogicalP() argument
4722 DCHECK(is_int20(opnd.offset())); in CmpLogicalP()
4724 clg(dst, opnd); in CmpLogicalP()
4726 CmpLogical32(dst, opnd); in CmpLogicalP()
4739 void MacroAssembler::Branch(Condition c, const Operand& opnd) { in Branch() argument
4740 intptr_t value = opnd.immediate(); in Branch()
4742 brc(c, opnd); in Branch()
4744 brcl(c, opnd); in Branch()
4907 void MacroAssembler::StoreP(const MemOperand& mem, const Operand& opnd, in StoreP() argument
4910 DCHECK(opnd.rmode_ == kRelocInfo_NONEPTR); in StoreP()
4914 mem.getIndexRegister().is(r0) && is_int16(opnd.imm_)) { in StoreP()
4916 mvghi(mem, opnd); in StoreP()
4918 mvhi(mem, opnd); in StoreP()
4921 LoadImmP(scratch, opnd); in StoreP()