Lines Matching refs:Bool
55 ST_IN HReg hregMIPS_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 0, 0); } in hregMIPS_GPR16()
56 ST_IN HReg hregMIPS_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 1, 1); } in hregMIPS_GPR17()
57 ST_IN HReg hregMIPS_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 2, 2); } in hregMIPS_GPR18()
58 ST_IN HReg hregMIPS_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 3, 3); } in hregMIPS_GPR19()
59 ST_IN HReg hregMIPS_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 4, 4); } in hregMIPS_GPR20()
60 ST_IN HReg hregMIPS_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 5, 5); } in hregMIPS_GPR21()
61 ST_IN HReg hregMIPS_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 6, 6); } in hregMIPS_GPR22()
63 ST_IN HReg hregMIPS_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 7, 7); } in hregMIPS_GPR12()
64 ST_IN HReg hregMIPS_GPR13 ( Bool mode64 ) { return GPR(mode64, 13, 8, 8); } in hregMIPS_GPR13()
65 ST_IN HReg hregMIPS_GPR14 ( Bool mode64 ) { return GPR(mode64, 14, 9, 9); } in hregMIPS_GPR14()
66 ST_IN HReg hregMIPS_GPR15 ( Bool mode64 ) { return GPR(mode64, 15, 10, 10); } in hregMIPS_GPR15()
67 ST_IN HReg hregMIPS_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 11, 11); } in hregMIPS_GPR24()
69 ST_IN HReg hregMIPS_F16 ( Bool mode64 ) { return FR (mode64, 16, 12, 12); } in hregMIPS_F16()
70 ST_IN HReg hregMIPS_F18 ( Bool mode64 ) { return FR (mode64, 18, 13, 13); } in hregMIPS_F18()
71 ST_IN HReg hregMIPS_F20 ( Bool mode64 ) { return FR (mode64, 20, 14, 14); } in hregMIPS_F20()
72 ST_IN HReg hregMIPS_F22 ( Bool mode64 ) { return FR (mode64, 22, 15, 15); } in hregMIPS_F22()
73 ST_IN HReg hregMIPS_F24 ( Bool mode64 ) { return FR (mode64, 24, 16, 16); } in hregMIPS_F24()
74 ST_IN HReg hregMIPS_F26 ( Bool mode64 ) { return FR (mode64, 26, 17, 17); } in hregMIPS_F26()
75 ST_IN HReg hregMIPS_F28 ( Bool mode64 ) { return FR (mode64, 28, 18, 18); } in hregMIPS_F28()
76 ST_IN HReg hregMIPS_F30 ( Bool mode64 ) { return FR (mode64, 30, 19, 19); } in hregMIPS_F30()
80 ST_IN HReg hregMIPS_D0 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D0()
82 ST_IN HReg hregMIPS_D1 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D1()
84 ST_IN HReg hregMIPS_D2 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D2()
86 ST_IN HReg hregMIPS_D3 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D3()
88 ST_IN HReg hregMIPS_D4 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D4()
90 ST_IN HReg hregMIPS_D5 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D5()
92 ST_IN HReg hregMIPS_D6 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D6()
94 ST_IN HReg hregMIPS_D7 ( Bool mode64 ) { vassert(!mode64); in hregMIPS_D7()
97 ST_IN HReg hregMIPS_HI ( Bool mode64 ) { return FR (mode64, 33, 20, 28); } in hregMIPS_HI()
98 ST_IN HReg hregMIPS_LO ( Bool mode64 ) { return FR (mode64, 34, 21, 29); } in hregMIPS_LO()
100 ST_IN HReg hregMIPS_GPR0 ( Bool mode64 ) { return GPR(mode64, 0, 22, 30); } in hregMIPS_GPR0()
101 ST_IN HReg hregMIPS_GPR1 ( Bool mode64 ) { return GPR(mode64, 1, 23, 31); } in hregMIPS_GPR1()
102 ST_IN HReg hregMIPS_GPR2 ( Bool mode64 ) { return GPR(mode64, 2, 24, 32); } in hregMIPS_GPR2()
103 ST_IN HReg hregMIPS_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 25, 33); } in hregMIPS_GPR3()
104 ST_IN HReg hregMIPS_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 26, 34); } in hregMIPS_GPR4()
105 ST_IN HReg hregMIPS_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 27, 35); } in hregMIPS_GPR5()
106 ST_IN HReg hregMIPS_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 28, 36); } in hregMIPS_GPR6()
107 ST_IN HReg hregMIPS_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 29, 37); } in hregMIPS_GPR7()
108 ST_IN HReg hregMIPS_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 30, 38); } in hregMIPS_GPR8()
109 ST_IN HReg hregMIPS_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 31, 39); } in hregMIPS_GPR9()
110 ST_IN HReg hregMIPS_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 32, 40); } in hregMIPS_GPR10()
111 ST_IN HReg hregMIPS_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 33, 41); } in hregMIPS_GPR11()
112 ST_IN HReg hregMIPS_GPR23 ( Bool mode64 ) { return GPR(mode64, 23, 34, 42); } in hregMIPS_GPR23()
113 ST_IN HReg hregMIPS_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 35, 43); } in hregMIPS_GPR25()
114 ST_IN HReg hregMIPS_GPR29 ( Bool mode64 ) { return GPR(mode64, 29, 36, 44); } in hregMIPS_GPR29()
115 ST_IN HReg hregMIPS_GPR31 ( Bool mode64 ) { return GPR(mode64, 31, 37, 45); } in hregMIPS_GPR31()
135 extern void ppHRegMIPS ( HReg, Bool );
194 extern void ppMIPSAMode(MIPSAMode *, Bool);
207 Bool syned;
216 extern void ppMIPSRH(MIPSRH *, Bool);
218 extern MIPSRH *MIPSRH_Imm(Bool, UShort);
248 Bool /* is the 2nd operand an immediate? */ );
258 Bool /* is the 2nd operand an immediate? */ ,
259 Bool /* is this a 32bit or 64bit op? */ );
267 extern const HChar *showMIPSMaccOp(MIPSMaccOp, Bool);
404 Bool sz32; /* mode64 has both 32 and 64bit shft */
417 Bool syned;
418 Bool sz32;
426 Bool widening; /* True => widening, False => non-widening */
427 Bool syned; /* signed/unsigned - meaningless if widenind = False */
428 Bool sz32;
434 Bool syned; /* signed/unsigned - meaningless if widenind = False */
435 Bool sz32;
461 Bool toFastEP; /* chain to the slow or fast point? */
519 Bool wrLR;
526 Bool syned;
559 Bool isLoad;
613 extern MIPSInstr *MIPSInstr_Shft(MIPSShftOp, Bool sz32, HReg, HReg, MIPSRH *);
615 extern MIPSInstr *MIPSInstr_Cmp(Bool, Bool, HReg, HReg, HReg, MIPSCondCode);
617 extern MIPSInstr *MIPSInstr_Mul(Bool syned, Bool hi32, Bool sz32, HReg,
619 extern MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg, HReg);
620 extern MIPSInstr *MIPSInstr_Madd(Bool, HReg, HReg);
621 extern MIPSInstr *MIPSInstr_Msub(Bool, HReg, HReg);
624 Bool mode64);
626 Bool mode64);
629 Bool mode64);
631 Bool mode64);
633 HReg expd, HReg data, Bool mode64);
639 MIPSCondCode cond, Bool toFastEP );
655 extern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *);
658 extern MIPSInstr *MIPSInstr_FpCftI(Bool fromI, Bool int32, HReg dst, HReg src);
669 extern MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr);
680 extern void ppMIPSInstr(const MIPSInstr *, Bool mode64);
684 extern void getRegUsage_MIPSInstr (HRegUsage *, const MIPSInstr *, Bool);
685 extern void mapRegs_MIPSInstr (HRegRemap *, MIPSInstr *, Bool mode64);
686 extern Bool isMove_MIPSInstr (const MIPSInstr *, HReg *, HReg *);
687 extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc,
689 Bool mode64,
697 HReg rreg, Int offset, Bool);
699 HReg rreg, Int offset, Bool);
701 extern const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 );
709 Bool chainingAllowed,
710 Bool addProfInc,
725 Bool mode64 );
731 Bool mode64 );
737 Bool mode64 );