247     if (instr->GXin.Mul.widening == False) {  in ppTILEGXInstr()
249       ppHRegTILEGX(instr->GXin.Mul.dst);  in ppTILEGXInstr()
251       ppHRegTILEGX(instr->GXin.Mul.srcL);  in ppTILEGXInstr()
253       ppHRegTILEGX(instr->GXin.Mul.srcR);  in ppTILEGXInstr()
256       vex_printf("%s ", instr->GXin.Mul.syned ? "mull32s" : "mull32u");  in ppTILEGXInstr()
257       ppHRegTILEGX(instr->GXin.Mul.dst);  in ppTILEGXInstr()
259       ppHRegTILEGX(instr->GXin.Mul.srcL);  in ppTILEGXInstr()
261       ppHRegTILEGX(instr->GXin.Mul.srcR);  in ppTILEGXInstr()
789   i->GXin.Mul.syned = syned;  in TILEGXInstr_Mul()
790   i->GXin.Mul.widening = wid; /* widen=True else False */  in TILEGXInstr_Mul()
791   i->GXin.Mul.sz32 = sz32;    /* True = 32 bits */  in TILEGXInstr_Mul()
792   i->GXin.Mul.dst = dst;  in TILEGXInstr_Mul()
793   i->GXin.Mul.srcL = srcL;  in TILEGXInstr_Mul()
794   i->GXin.Mul.srcR = srcR;  in TILEGXInstr_Mul()
972     addHRegUse(u, HRmWrite, i->GXin.Mul.dst);  in getRegUsage_TILEGXInstr()
973     addHRegUse(u, HRmRead, i->GXin.Mul.srcL);  in getRegUsage_TILEGXInstr()
974     addHRegUse(u, HRmRead, i->GXin.Mul.srcR);  in getRegUsage_TILEGXInstr()
1124     mapReg(m, &i->GXin.Mul.dst);  in mapRegs_TILEGXInstr()
1125     mapReg(m, &i->GXin.Mul.srcL);  in mapRegs_TILEGXInstr()
1126     mapReg(m, &i->GXin.Mul.srcR);  in mapRegs_TILEGXInstr()
2030     Bool syned = i->GXin.Mul.syned;  in emit_TILEGXInstr()
2031     Bool widening = i->GXin.Mul.widening;  in emit_TILEGXInstr()
2032     Bool sz32 = i->GXin.Mul.sz32;  in emit_TILEGXInstr()
2033     UInt r_srcL = iregNo(i->GXin.Mul.srcL);  in emit_TILEGXInstr()
2034     UInt r_srcR = iregNo(i->GXin.Mul.srcR);  in emit_TILEGXInstr()
2035     UInt r_dst = iregNo(i->GXin.Mul.dst);  in emit_TILEGXInstr()