| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 215 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, in getLdStUImm12OpValue()
236 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, in getAdrLabelOpValue()
262 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, in getAddSubImmOpValue()
290 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getCondBranchTargetOpValue()
311 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, in getLoadLiteralOpValue()
331 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, in getMemExtendOpValue()
340 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, in getMoveWideImmOpValue()
360 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getTestBranchTargetOpValue()
381 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
409 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, in getVecShifterOpValue()
[all …]
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, in getLdStmModeOpValue()
558 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, in EncodeAddrModeOpValues()
587 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
625 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLTargetOpValue()
638 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLXTargetOpValue()
650 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBRTargetOpValue()
662 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBCCTargetOpValue()
674 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbCBTargetOpValue()
703 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
717 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getARMBranchTargetOpValue()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 388 unsigned OpIdx = 0; in ExpandVLD() local
453 unsigned OpIdx = 0; in ExpandVST() local
507 unsigned OpIdx = 0; in ExpandLaneOp() local
590 unsigned OpIdx = 0; in ExpandVTBL() local
1134 unsigned OpIdx = 0; in ExpandMI() local
1165 unsigned OpIdx = 0; in ExpandMI() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AddressTypePromotion.cpp | 209 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand()
314 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
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| D | AArch64PromoteConstant.cpp | 240 unsigned OpIdx) { in shouldConvertUse()
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| D | AArch64InstrInfo.cpp | 715 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx; in UpdateOperandRegClass() local
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| /external/llvm/utils/TableGen/ |
| D | CodeEmitterGen.cpp | 87 unsigned OpIdx; in AddCodeToMergeInOperand() local
193 unsigned OpIdx; in getInstructionCase() local
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| D | CodeGenInstruction.cpp | 137 unsigned OpIdx; in getOperandNamed() local
173 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local
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| D | FixedLenDecoderEmitter.cpp | 1781 unsigned OpIdx; in populateInstruction() local
1812 unsigned OpIdx; in populateInstruction() local
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| D | AsmWriterEmitter.cpp | 649 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { in addOperand()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1054 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx()
1083 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint()
1137 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, in getRegClassConstraintEffectForVRegImpl()
1149 unsigned OpIdx, const TargetRegisterClass *CurRC, in getRegClassConstraintEffect()
1845 unsigned OpIdx = DeadOps.back(); in addRegisterKilled() local
1909 unsigned OpIdx = DeadOps.back(); in addRegisterDead() local
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| D | ExecutionDepsFix.cpp | 473 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence()
559 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
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| D | TargetInstrInfo.cpp | 677 unsigned OpIdx[4][4] = { in reassociateOps() local
1150 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in getRegSequenceInputs() local
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| D | PeepholeOptimizer.cpp | 1704 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast() local
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 59 int OpIdx; member
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 61 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI() local
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| D | AMDGPUOpenCLImageTypeLoweringPass.cpp | 121 GetArgMD(MDNode *KernelMDNode, unsigned OpIdx) { in GetArgMD()
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| D | SIInstrInfo.cpp | 1535 for (int OpIdx : OpIndices) { in verifyInstruction() local
1803 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, in isOperandLegal()
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| D | AMDGPUISelDAGToDAG.cpp | 188 unsigned OpIdx = Desc.getNumDefs() + OpNo; in getOperandRegClass() local
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 170 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; in getItineraryLatency() local
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx, in EmitSrc()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 626 unsigned OpIdx, SDep& dep) const{ in computeOperandLatency()
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| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| D | RuntimeDyldChecker.cpp | 254 unsigned OpIdx = OpIdxExpr.getValue(); in evalDecodeOperand() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2286 unsigned OpIdx = NElts - i - 1; in LowerBUILD_VECTOR() local
2317 unsigned OpIdx = NElts - i - 1; in LowerBUILD_VECTOR() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | Reassociate.cpp | 582 for (unsigned OpIdx = 0; OpIdx < 2; ++OpIdx) { // Visit operands. in LinearizeExprTree() local
|