| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 525 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
547 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
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| D | LegalizeIntegerTypes.cpp | 2115 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2128 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
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| D | LegalizeVectorTypes.cpp | 1167 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
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| D | DAGCombiner.cpp | 5206 SDValue Lo, Hi, LL, LH, RL, RH; in SplitVSETCC() local
5621 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH; in visitVSELECT() local
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| /external/deqp/framework/common/ |
| D | tcuCompressedTexture.cpp | 674 const deUint8 RH = extend6To8((deUint8)((RH1 << 1) | RH2)); in decompressETC2Block() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1621 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1708 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 705 SDValue LH, RH; in TryExpandADDWithMul() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2825 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI() local
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| /external/v8/test/mjsunit/asm/poppler/ |
| D | poppler.js | 7325 …r p=0,q=0,r=0,s=0,t=0,u=0,v=0,w=0,x=0,y=0,z=0,A=0,B=0,C=0,D=0,E=0,F=0,G=0,H=0,I=0,J=0,K=0,L=0,M=0,…
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