| /external/valgrind/none/tests/mips64/ |
| D | macro_int.h | 1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \ argument
19 #define TEST2(instruction, RSval, imm, RT, RS) \ argument
35 #define TEST3(instruction, RSval, RD, RS) \ argument
51 #define TEST4(instruction, RSval, RTval, RS, RT) \ argument
71 #define TEST5(instruction, RSval, RTval, RS, RT) \ argument
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| D | branches.c | 130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
201 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
224 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument
246 #define TESTINST6l(instruction, RDval, RSval, RD, RS) \ argument
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| D | branch_and_jump_instructions.c | 107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
130 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument
152 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
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| D | cvm_ins.c | 70 #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1) \ argument
85 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \ argument
101 #define TESTINST3(instruction, RSVal, RT, RS, imm) \ argument
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| D | load_store_multiple.c | 23 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
53 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
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| D | move_instructions.c | 178 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
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| /external/valgrind/none/tests/mips32/ |
| D | mips32_dsp.c | 76 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
119 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
137 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
155 #define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \ argument
183 #define TESTDSPINST_AC_RS_RT_NODSPC(instruction, ac, RSval, RTval, HIval, \ argument
230 #define TESTDSPINST_EXTV(instruction, ac, RT, HIval, LOval, RS, RSval, pos) \ argument
254 #define TESTDSPINST_INSV(instruction, RTval, RSval, RT, RS, _pos, _size) \ argument
275 #define TESTDSPINST_LWX(index, RT, RS) \ argument
290 #define TESTDSPINST_LHX(index, RT, RS) \ argument
305 #define TESTDSPINST_LBUX(index, RT, RS) \ argument
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| D | mips32_dspr2.c | 92 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
134 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
152 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
170 #define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \ argument
245 #define TESTDSPINST_EXTV(instruction, ac, RT, HIval, LOval, RS, RSval, pos) \ argument
269 #define TESTDSPINST_INSV(instruction, RTval, RSval, RT, RS, _pos, _size) \ argument
290 #define TESTDSPINST_LWX(index, RT, RS) \ argument
305 #define TESTDSPINST_LHX(index, RT, RS) \ argument
320 #define TESTDSPINST_LBUX(index, RT, RS) \ argument
355 #define TESTDSPINST_MTHLIP(instruction, ac, HIval, LOval, RSval, RS, pos) \ argument
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| D | MIPS32int.c | 3 #define TESTINST1(instruction, RSval, RTval, RD, RS, RT) \ argument
20 #define TESTINST2(instruction, RSval, imm, RT, RS) \ argument
35 #define TESTINST3(instruction, RSval, RD, RS) \ argument
50 #define TESTINST3a(instruction, RSval, RTval, RS, RT) \ argument
71 #define TESTINST4(instruction, RTval, RSval, RT, RS, pos, size) \ argument
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| D | branches.c | 114 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
135 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
155 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
179 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
200 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument
220 #define TESTINST6l(instruction, RDval, RSval, RD, RS) \ argument
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| D | LoadStore.c | 24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
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| D | LoadStore1.c | 24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
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| /external/valgrind/none/tests/arm/ |
| D | v6intARM.c | 70 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ argument
100 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
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| D | v6media.c | 79 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ argument
109 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
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| D | v6intThumb.c | 162 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, cvin) \ argument
190 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ argument
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| /external/llvm/include/llvm/DebugInfo/DWARF/ |
| D | DWARFCompileUnit.h | 20 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in DWARFCompileUnit()
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| D | DWARFTypeUnit.h | 23 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in DWARFTypeUnit()
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| D | DWARFUnit.h | 86 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in parseImpl()
166 void setRangesSection(StringRef RS, uint32_t Base) { in setRangesSection()
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| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | MallocChecker.cpp | 93 static RefState getAllocatedOfSizeZero(const RefState *RS) { in getAllocatedOfSizeZero()
103 static RefState getEscaped(const RefState *RS) { in getEscaped()
894 const RefState *RS = State->get<RegionState>(Sym); in ProcessZeroAllocation() local
1498 const RefState *RS = C.getState()->get<RegionState>(Sym); in getCheckIfTracked() local
1665 const RefState *RS, in ReportMismatchedDealloc()
2057 const RefState *RS = C.getState()->get<RegionState>(Sym); in reportLeak() local
2125 RegionStateTy RS = state->get<RegionState>(); in checkDeadSymbols() local
2286 const RefState *RS = C.getState()->get<RegionState>(Sym); in isReleased() local
2305 if (const RefState *RS = C.getState()->get<RegionState>(Sym)) { in checkUseZeroAllocated() local
2338 RegionStateTy RS = state->get<RegionState>(); in evalAssume() local
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| D | ReturnPointerRangeChecker.cpp | 35 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt()
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| D | ReturnUndefChecker.cpp | 39 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt()
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| /external/llvm/lib/CodeGen/ |
| D | ShrinkWrap.cpp | 270 RegScavenger *RS) { in updateSaveRestorePoints()
398 std::unique_ptr<RegScavenger> RS( in runOnMachineFunction() local
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| D | BranchFolding.h | 99 RegScavenger *RS; variable
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 96 int Offset, RegScavenger *RS ) { in InsertFPConstInst()
164 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 123 const RegisterSet &RS; member
889 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) { in isTransparentCopy()
1234 BitTracker::RegisterRef RS) { in usedBitsEqual()
1283 BitTracker::RegisterRef RS = Op; in processBlock() local
1601 BitTracker::RegisterRef RS = MI.getOperand(1); in propagateRegCopy() local
1633 BitTracker::RegisterRef RS = MI.getOperand(SrcX); in propagateRegCopy() local
1827 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf() local
1871 BitTracker::RegisterRef RS = MI->getOperand(2); in genStoreImmediate() local
2035 BitTracker::RegisterRef RS = Op; in genExtractLow() local
2073 BitTracker::RegisterRef RS = MI->getOperand(1); in simplifyTstbit() local
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