1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The LiveRangeEdit class represents changes done to a virtual register when it 11 // is spilled or split. 12 // 13 // The parent register is never changed. Instead, a number of new virtual 14 // registers are created and added to the newRegs vector. 15 // 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H 19 #define LLVM_CODEGEN_LIVERANGEEDIT_H 20 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallPtrSet.h" 24 #include "llvm/Analysis/AliasAnalysis.h" 25 #include "llvm/CodeGen/LiveInterval.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/Target/TargetMachine.h" 28 #include "llvm/Target/TargetSubtargetInfo.h" 29 30 namespace llvm { 31 32 class LiveIntervals; 33 class MachineBlockFrequencyInfo; 34 class MachineLoopInfo; 35 class VirtRegMap; 36 37 class LiveRangeEdit : private MachineRegisterInfo::Delegate { 38 public: 39 /// Callback methods for LiveRangeEdit owners. 40 class Delegate { 41 virtual void anchor(); 42 public: 43 /// Called immediately before erasing a dead machine instruction. LRE_WillEraseInstruction(MachineInstr * MI)44 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {} 45 46 /// Called when a virtual register is no longer used. Return false to defer 47 /// its deletion from LiveIntervals. LRE_CanEraseVirtReg(unsigned)48 virtual bool LRE_CanEraseVirtReg(unsigned) { return true; } 49 50 /// Called before shrinking the live range of a virtual register. LRE_WillShrinkVirtReg(unsigned)51 virtual void LRE_WillShrinkVirtReg(unsigned) {} 52 53 /// Called after cloning a virtual register. 54 /// This is used for new registers representing connected components of Old. LRE_DidCloneVirtReg(unsigned New,unsigned Old)55 virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {} 56 ~Delegate()57 virtual ~Delegate() {} 58 }; 59 60 private: 61 LiveInterval *Parent; 62 SmallVectorImpl<unsigned> &NewRegs; 63 MachineRegisterInfo &MRI; 64 LiveIntervals &LIS; 65 VirtRegMap *VRM; 66 const TargetInstrInfo &TII; 67 Delegate *const TheDelegate; 68 69 /// FirstNew - Index of the first register added to NewRegs. 70 const unsigned FirstNew; 71 72 /// ScannedRemattable - true when remattable values have been identified. 73 bool ScannedRemattable; 74 75 /// Remattable - Values defined by remattable instructions as identified by 76 /// tii.isTriviallyReMaterializable(). 77 SmallPtrSet<const VNInfo*,4> Remattable; 78 79 /// Rematted - Values that were actually rematted, and so need to have their 80 /// live range trimmed or entirely removed. 81 SmallPtrSet<const VNInfo*,4> Rematted; 82 83 /// scanRemattable - Identify the Parent values that may rematerialize. 84 void scanRemattable(AliasAnalysis *aa); 85 86 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 87 /// OrigIdx are also available with the same value at UseIdx. 88 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, 89 SlotIndex UseIdx) const; 90 91 /// foldAsLoad - If LI has a single use and a single def that can be folded as 92 /// a load, eliminate the register by folding the def into the use. 93 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead); 94 95 typedef SetVector<LiveInterval*, 96 SmallVector<LiveInterval*, 8>, 97 SmallPtrSet<LiveInterval*, 8> > ToShrinkSet; 98 /// Helper for eliminateDeadDefs. 99 void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink); 100 101 /// MachineRegisterInfo callback to notify when new virtual 102 /// registers are created. 103 void MRI_NoteNewVirtualRegister(unsigned VReg) override; 104 105 /// \brief Check if MachineOperand \p MO is a last use/kill either in the 106 /// main live range of \p LI or in one of the matching subregister ranges. 107 bool useIsKill(const LiveInterval &LI, const MachineOperand &MO) const; 108 109 public: 110 /// Create a LiveRangeEdit for breaking down parent into smaller pieces. 111 /// @param parent The register being spilled or split. 112 /// @param newRegs List to receive any new registers created. This needn't be 113 /// empty initially, any existing registers are ignored. 114 /// @param MF The MachineFunction the live range edit is taking place in. 115 /// @param lis The collection of all live intervals in this function. 116 /// @param vrm Map of virtual registers to physical registers for this 117 /// function. If NULL, no virtual register map updates will 118 /// be done. This could be the case if called before Regalloc. 119 LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<unsigned> &newRegs, 120 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm, 121 Delegate *delegate = nullptr) Parent(parent)122 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis), 123 VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), 124 TheDelegate(delegate), FirstNew(newRegs.size()), 125 ScannedRemattable(false) { 126 MRI.setDelegate(this); 127 } 128 ~LiveRangeEdit()129 ~LiveRangeEdit() override { MRI.resetDelegate(this); } 130 getParent()131 LiveInterval &getParent() const { 132 assert(Parent && "No parent LiveInterval"); 133 return *Parent; 134 } getReg()135 unsigned getReg() const { return getParent().reg; } 136 137 /// Iterator for accessing the new registers added by this edit. 138 typedef SmallVectorImpl<unsigned>::const_iterator iterator; begin()139 iterator begin() const { return NewRegs.begin()+FirstNew; } end()140 iterator end() const { return NewRegs.end(); } size()141 unsigned size() const { return NewRegs.size()-FirstNew; } empty()142 bool empty() const { return size() == 0; } get(unsigned idx)143 unsigned get(unsigned idx) const { return NewRegs[idx+FirstNew]; } 144 regs()145 ArrayRef<unsigned> regs() const { 146 return makeArrayRef(NewRegs).slice(FirstNew); 147 } 148 149 /// createEmptyIntervalFrom - Create a new empty interval based on OldReg. 150 LiveInterval &createEmptyIntervalFrom(unsigned OldReg); 151 152 /// createFrom - Create a new virtual register based on OldReg. 153 unsigned createFrom(unsigned OldReg); 154 155 /// create - Create a new register with the same class and original slot as 156 /// parent. createEmptyInterval()157 LiveInterval &createEmptyInterval() { 158 return createEmptyIntervalFrom(getReg()); 159 } 160 create()161 unsigned create() { 162 return createFrom(getReg()); 163 } 164 165 /// anyRematerializable - Return true if any parent values may be 166 /// rematerializable. 167 /// This function must be called before any rematerialization is attempted. 168 bool anyRematerializable(AliasAnalysis*); 169 170 /// checkRematerializable - Manually add VNI to the list of rematerializable 171 /// values if DefMI may be rematerializable. 172 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, 173 AliasAnalysis*); 174 175 /// Remat - Information needed to rematerialize at a specific location. 176 struct Remat { 177 VNInfo *ParentVNI; // parent_'s value at the remat location. 178 MachineInstr *OrigMI; // Instruction defining ParentVNI. RematRemat179 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(nullptr) {} 180 }; 181 182 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at 183 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 184 /// When cheapAsAMove is set, only cheap remats are allowed. 185 bool canRematerializeAt(Remat &RM, 186 SlotIndex UseIdx, 187 bool cheapAsAMove); 188 189 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an 190 /// instruction into MBB before MI. The new instruction is mapped, but 191 /// liveness is not updated. 192 /// Return the SlotIndex of the new instruction. 193 SlotIndex rematerializeAt(MachineBasicBlock &MBB, 194 MachineBasicBlock::iterator MI, 195 unsigned DestReg, 196 const Remat &RM, 197 const TargetRegisterInfo&, 198 bool Late = false); 199 200 /// markRematerialized - explicitly mark a value as rematerialized after doing 201 /// it manually. markRematerialized(const VNInfo * ParentVNI)202 void markRematerialized(const VNInfo *ParentVNI) { 203 Rematted.insert(ParentVNI); 204 } 205 206 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. didRematerialize(const VNInfo * ParentVNI)207 bool didRematerialize(const VNInfo *ParentVNI) const { 208 return Rematted.count(ParentVNI); 209 } 210 211 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 212 /// to erase it from LIS. 213 void eraseVirtReg(unsigned Reg); 214 215 /// eliminateDeadDefs - Try to delete machine instructions that are now dead 216 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed 217 /// and further dead efs to be eliminated. 218 /// RegsBeingSpilled lists registers currently being spilled by the register 219 /// allocator. These registers should not be split into new intervals 220 /// as currently those new intervals are not guaranteed to spill. 221 void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead, 222 ArrayRef<unsigned> RegsBeingSpilled = None); 223 224 /// calculateRegClassAndHint - Recompute register class and hint for each new 225 /// register. 226 void calculateRegClassAndHint(MachineFunction&, 227 const MachineLoopInfo&, 228 const MachineBlockFrequencyInfo&); 229 }; 230 231 } 232 233 #endif 234