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Searched defs:VReg (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyMachineFunctionInfo.h56 void stackifyVReg(unsigned VReg) { in stackifyVReg()
61 bool isVRegStackified(unsigned VReg) const { in isVRegStackified()
68 void setWAReg(unsigned VReg, unsigned WAReg) { in setWAReg()
82 void addWAReg(unsigned VReg, unsigned WAReg) { in addWAReg()
DWebAssemblyRegColoring.cpp65 unsigned VReg) { in computeWeight()
99 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
DWebAssemblyRegNumbering.cpp91 unsigned VReg = TargetRegisterInfo::index2VirtReg(VRegIdx); in runOnMachineFunction() local
DWebAssemblyRegStackify.cpp240 unsigned VReg = MO.getReg(); in runOnMachineFunction() local
DWebAssemblyAsmPrinter.cpp173 unsigned VReg = TargetRegisterInfo::index2VirtReg(Idx); in EmitFunctionBodyStart() local
/external/v8/test/unittests/compiler/
Dinstruction-sequence-unittest.h23 struct VReg { struct
24 VReg() : value_(kNoValue) {} in VReg() argument
25 VReg(PhiInstruction* phi) : value_(phi->virtual_register()) {} // NOLINT in VReg() argument
26 explicit VReg(int value) : value_(value) {} in VReg() function
30 typedef std::pair<VReg, VReg> VRegPair; argument
/external/llvm/lib/CodeGen/
DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createEmptyIntervalFrom() local
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
352 unsigned VReg = LI->reg; in eliminateDeadDefs() local
395 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg) in MRI_NoteNewVirtualRegister()
DRegAllocPBQP.cpp298 unsigned VReg = G.getNodeMetadata(NId).getVReg(); in apply() local
566 unsigned VReg = Worklist.back(); in initializeGraph() local
628 void RegAllocPBQP::spillVReg(unsigned VReg, in spillVReg()
673 unsigned VReg = G.getNodeMetadata(NId).getVReg(); in mapPBQPToRegAlloc() local
815 unsigned VReg = G.getNodeMetadata(NId).getVReg(); in PrintNodeInfo() local
DLiveIntervalUnion.cpp150 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
DCallingConvLower.cpp246 unsigned VReg = MF.addLiveIn(PReg, RC); in analyzeMustTailForwardedRegisters() local
/external/llvm/include/llvm/CodeGen/
DRegAllocPBQP.h154 void setNodeIdForVReg(unsigned VReg, GraphBase::NodeId NId) { in setNodeIdForVReg()
158 GraphBase::NodeId getNodeIdForVReg(unsigned VReg) const { in getNodeIdForVReg()
165 void eraseNodeIdForVReg(unsigned VReg) { in eraseNodeIdForVReg()
260 void setVReg(unsigned VReg) { this->VReg = VReg; } in setVReg()
320 unsigned VReg; variable
DLiveIntervalUnion.h125 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query()
141 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init()
DMachineRegisterInfo.h178 bool shouldTrackSubRegLiveness(unsigned VReg) const { in shouldTrackSubRegLiveness()
599 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint()
607 void setSimpleHint(unsigned VReg, unsigned PrefReg) { in setSimpleHint()
614 getRegAllocationHint(unsigned VReg) const { in getRegAllocationHint()
621 unsigned getSimpleHint(unsigned VReg) const { in getSimpleHint()
DCallingConvLower.h168 unsigned VReg; member
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local
321 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
442 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
495 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitSubregNode() local
588 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
DFunctionLoweringInfo.cpp519 unsigned &VReg = I.first->second; in getCatchPadExceptionPointerVReg() local
/external/llvm/lib/Target/NVPTX/InstPrinter/
DNVPTXInstPrinter.cpp66 unsigned VReg = RegNo & 0x0FFFFFFF; in printRegName() local
/external/llvm/lib/CodeGen/MIRParser/
DMIRParser.cpp349 for (const auto &VReg : YamlMF.VirtualRegisters) { in initializeRegisterInfo() local
377 unsigned VReg = 0; in initializeRegisterInfo() local
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1071 unsigned VReg = in LowerFormalArguments() local
1076 unsigned VReg = in LowerFormalArguments() local
1084 unsigned VReg = in LowerFormalArguments() local
1091 unsigned VReg = in LowerFormalArguments() local
1099 unsigned VReg = in LowerFormalArguments() local
1106 unsigned VReg = in LowerFormalArguments() local
1112 unsigned VReg = in LowerFormalArguments() local
DHexagonStoreWidening.cpp451 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC); in createWideStores() local
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2980 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_32SVR4() local
2999 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_32SVR4() local
3194 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
3230 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
3254 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
3267 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
3291 unsigned VReg; in LowerFormalArguments_64SVR4() local
3312 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
3352 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ? in LowerFormalArguments_64SVR4() local
3385 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC); in LowerFormalArguments_64SVR4() local
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp283 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { in removeCopies()
296 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, in canFoldIntoCSel()
2950 unsigned VReg = MI->getOperand(0).getReg(); in optimizeCondBranch() local
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp219 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); in LowerFormalArguments() local
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp508 unsigned VReg = 0; in eliminateFrameIndex() local
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp456 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32() local
568 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32() local
618 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64() local
689 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64() local

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