| /external/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
139 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
157 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
171 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, in query()
179 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
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| D | RegAllocFast.cpp | 72 unsigned VirtReg; // Virtual register number. member
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
256 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
410 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
426 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
453 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
474 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
507 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
[all …]
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| D | RegAllocGreedy.cpp | 214 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
492 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
504 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
616 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
660 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
723 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
805 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
856 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1345 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1375 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost()
[all …]
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| D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
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| D | VirtRegMap.cpp | 84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
288 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
371 unsigned VirtReg = MO.getReg(); in rewrite() local
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| D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
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| D | RegAllocBasic.cpp | 166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
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| D | RegAllocBase.cpp | 88 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
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| D | RegisterCoalescer.h | 66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
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| D | LiveDebugVariables.cpp | 476 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
482 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
916 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
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| D | PHIElimination.cpp | 203 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined()
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| D | TargetRegisterInfo.cpp | 337 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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| D | MachineBasicBlock.cpp | 391 unsigned VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
398 unsigned VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
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| D | InlineSpiller.cpp | 856 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, in reMaterializeFor()
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveIntervalUnion.h | 88 void unify(LiveInterval &VirtReg) { in unify()
94 void extract(LiveInterval &VirtReg) { in extract()
113 LiveInterval *VirtReg; variable
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| D | VirtRegMap.h | 151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
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| D | ScheduleDAGInstrs.h | 34 unsigned VirtReg; member
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1097 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in replacePredRegPseudoSpillCode() local
1124 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in replacePredRegPseudoSpillCode() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 224 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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