1 //===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Utility functions for Hexagon specific MCInst queries
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
16
17 #include "HexagonMCExpr.h"
18 #include "llvm/MC/MCInst.h"
19
20 namespace llvm {
21 class HexagonMCChecker;
22 class MCContext;
23 class MCInstrDesc;
24 class MCInstrInfo;
25 class MCInst;
26 class MCOperand;
27 class MCSubtargetInfo;
28 namespace HexagonII {
29 enum class MemAccessSize;
30 }
31 class DuplexCandidate {
32 public:
33 unsigned packetIndexI, packetIndexJ, iClass;
DuplexCandidate(unsigned i,unsigned j,unsigned iClass)34 DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
35 : packetIndexI(i), packetIndexJ(j), iClass(iClass) {}
36 };
37 namespace HexagonMCInstrInfo {
38 size_t const innerLoopOffset = 0;
39 int64_t const innerLoopMask = 1 << innerLoopOffset;
40
41 size_t const outerLoopOffset = 1;
42 int64_t const outerLoopMask = 1 << outerLoopOffset;
43
44 // do not reorder memory load/stores by default load/stores are re-ordered
45 // and by default loads can be re-ordered
46 size_t const memReorderDisabledOffset = 2;
47 int64_t const memReorderDisabledMask = 1 << memReorderDisabledOffset;
48
49 // allow re-ordering of memory stores by default stores cannot be re-ordered
50 size_t const memStoreReorderEnabledOffset = 3;
51 int64_t const memStoreReorderEnabledMask = 1 << memStoreReorderEnabledOffset;
52
53 size_t const bundleInstructionsOffset = 1;
54
55 void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);
56 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
57 MCInst const &MCI);
58
59 // Returns a iterator range of instructions in this bundle
60 iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
61
62 // Returns the number of instructions in the bundle
63 size_t bundleSize(MCInst const &MCI);
64
65 // Put the packet in to canonical form, compound, duplex, pad, and shuffle
66 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
67 MCContext &Context, MCInst &MCB,
68 HexagonMCChecker *Checker);
69
70 // Clamp off upper 26 bits of extendable operand for emission
71 void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
72
73 MCInst createBundle();
74
75 // Return the extender for instruction at Index or nullptr if none
76 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
77 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
78 MCInst const &MCI, bool MustExtend);
79
80 // Create a duplex instruction given the two subinsts
81 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
82 MCInst const &inst1);
83 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
84 MCOperand const &MO);
85
86 // Convert this instruction in to a duplex subinst
87 MCInst deriveSubInst(MCInst const &Inst);
88
89 // Return the extender for instruction at Index or nullptr if none
90 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
91
92 // Return memory access size
93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
94 MCInst const &MCI);
95
96 // Return number of bits in the constant extended operand.
97 unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI);
98
99 // Return constant extended operand number.
100 unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI);
101
102 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
103
104 // Return which duplex group this instruction belongs to
105 unsigned getDuplexCandidateGroup(MCInst const &MI);
106
107 // Return a list of all possible instruction duplex combinations
108 SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII,
109 MCInst const &MCB);
110
111 // Return the index of the extendable operand
112 unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
113
114 // Return a reference to the extendable operand
115 MCOperand const &getExtendableOperand(MCInstrInfo const &MCII,
116 MCInst const &MCI);
117
118 // Return the implicit alignment of the extendable operand
119 unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
120
121 // Return the number of logical bits of the extendable operand
122 unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
123
124 // Return the max value that a constant extendable operand can have
125 // without being extended.
126 int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
127
128 // Return the min value that a constant extendable operand can have
129 // without being extended.
130 int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
131
132 // Return instruction name
133 char const *getName(MCInstrInfo const &MCII, MCInst const &MCI);
134
135 // Return the operand index for the new value.
136 unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
137
138 // Return the operand that consumes or produces a new value.
139 MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
140 unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
141 MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
142 MCInst const &MCI);
143
144 int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI);
145
146 // Return the Hexagon ISA class for the insn.
147 unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
148
149 /// Return the slots used by the insn.
150 unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
151 MCInst const &MCI);
152
153 // Does the packet have an extender for the instruction at Index
154 bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
155
156 bool hasImmExt(MCInst const &MCI);
157
158 // Return whether the instruction is a legal new-value producer.
159 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
160 bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
161
162 // Return the instruction at Index
163 MCInst const &instruction(MCInst const &MCB, size_t Index);
164
165 // Returns whether this MCInst is a wellformed bundle
166 bool isBundle(MCInst const &MCI);
167
168 // Return whether the insn is an actual insn.
169 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
170 bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
171
172 // Return the duplex iclass given the two duplex classes
173 unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
174
175 int64_t minConstant(MCInst const &MCI, size_t Index);
176 template <unsigned N, unsigned S>
inRange(MCInst const & MCI,size_t Index)177 bool inRange(MCInst const &MCI, size_t Index) {
178 return isShiftedUInt<N, S>(minConstant(MCI, Index));
179 }
180 template <unsigned N, unsigned S>
inSRange(MCInst const & MCI,size_t Index)181 bool inSRange(MCInst const &MCI, size_t Index) {
182 return isShiftedInt<N, S>(minConstant(MCI, Index));
183 }
inRange(MCInst const & MCI,size_t Index)184 template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
185 return isUInt<N>(minConstant(MCI, Index));
186 }
187
188 // Return whether the instruction needs to be constant extended.
189 bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
190
191 // Is this double register suitable for use in a duplex subinst
192 bool isDblRegForSubInst(unsigned Reg);
193
194 // Is this a duplex instruction
195 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
196
197 // Can these instructions be duplexed
198 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
199
200 // Can these duplex classes be combine in to a duplex instruction
201 bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
202
203 // Return true if the insn may be extended based on the operand value.
204 bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
205
206 // Return whether the instruction must be always extended.
207 bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
208
209 /// Return whether it is a floating-point insn.
210 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
211
212 // Returns whether this instruction is an immediate extender
213 bool isImmext(MCInst const &MCI);
214
215 // Returns whether this bundle is an endloop0
216 bool isInnerLoop(MCInst const &MCI);
217
218 // Is this an integer register
219 bool isIntReg(unsigned Reg);
220
221 // Is this register suitable for use in a duplex subinst
222 bool isIntRegForSubInst(unsigned Reg);
223 bool isMemReorderDisabled(MCInst const &MCI);
224 bool isMemStoreReorderEnabled(MCInst const &MCI);
225
226 // Return whether the insn is a new-value consumer.
227 bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
228
229 // Return true if the operand can be constant extended.
230 bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI,
231 unsigned short OperandNum);
232
233 // Can these two instructions be duplexed
234 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
235 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
236 bool bisReversable);
237
238 // Returns whether this bundle is an endloop1
239 bool isOuterLoop(MCInst const &MCI);
240
241 // Return whether this instruction is predicated
242 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
243 bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
244 bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
245
246 // Return whether the predicate sense is true
247 bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
248
249 // Is this a predicate register
250 bool isPredReg(unsigned Reg);
251
252 // Return whether the insn is a prefix.
253 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
254
255 // Return whether the insn is solo, i.e., cannot be in a packet.
256 bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
257
258 /// Return whether the insn can be packaged only with A and X-type insns.
259 bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
260
261 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
262 bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI);
263 bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
264
265 // Pad the bundle with nops to satisfy endloop requirements
266 void padEndloop(MCContext &Context, MCInst &MCI);
267
268 bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
269
270 // Replace the instructions inside MCB, represented by Candidate
271 void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate);
272
273 // Marks a bundle as endloop0
274 void setInnerLoop(MCInst &MCI);
275 void setMemReorderDisabled(MCInst &MCI);
276 void setMemStoreReorderEnabled(MCInst &MCI);
277
278 // Marks a bundle as endloop1
279 void setOuterLoop(MCInst &MCI);
280
281 // Would duplexing this instruction create a requirement to extend
282 bool subInstWouldBeExtended(MCInst const &potentialDuplex);
283
284 // Attempt to find and replace compound pairs
285 void tryCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
286 }
287 }
288
289 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
290