1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // MIPS-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(MipsAdd) \ 16 V(MipsAddOvf) \ 17 V(MipsSub) \ 18 V(MipsSubOvf) \ 19 V(MipsMul) \ 20 V(MipsMulHigh) \ 21 V(MipsMulHighU) \ 22 V(MipsDiv) \ 23 V(MipsDivU) \ 24 V(MipsMod) \ 25 V(MipsModU) \ 26 V(MipsAnd) \ 27 V(MipsOr) \ 28 V(MipsNor) \ 29 V(MipsXor) \ 30 V(MipsClz) \ 31 V(MipsCtz) \ 32 V(MipsPopcnt) \ 33 V(MipsLsa) \ 34 V(MipsShl) \ 35 V(MipsShr) \ 36 V(MipsSar) \ 37 V(MipsShlPair) \ 38 V(MipsShrPair) \ 39 V(MipsSarPair) \ 40 V(MipsExt) \ 41 V(MipsIns) \ 42 V(MipsRor) \ 43 V(MipsMov) \ 44 V(MipsTst) \ 45 V(MipsCmp) \ 46 V(MipsCmpS) \ 47 V(MipsAddS) \ 48 V(MipsSubS) \ 49 V(MipsSubPreserveNanS) \ 50 V(MipsMulS) \ 51 V(MipsDivS) \ 52 V(MipsModS) \ 53 V(MipsAbsS) \ 54 V(MipsSqrtS) \ 55 V(MipsMaxS) \ 56 V(MipsMinS) \ 57 V(MipsCmpD) \ 58 V(MipsAddD) \ 59 V(MipsSubD) \ 60 V(MipsSubPreserveNanD) \ 61 V(MipsMulD) \ 62 V(MipsDivD) \ 63 V(MipsModD) \ 64 V(MipsAbsD) \ 65 V(MipsSqrtD) \ 66 V(MipsMaxD) \ 67 V(MipsMinD) \ 68 V(MipsAddPair) \ 69 V(MipsSubPair) \ 70 V(MipsMulPair) \ 71 V(MipsFloat32RoundDown) \ 72 V(MipsFloat32RoundTruncate) \ 73 V(MipsFloat32RoundUp) \ 74 V(MipsFloat32RoundTiesEven) \ 75 V(MipsFloat64RoundDown) \ 76 V(MipsFloat64RoundTruncate) \ 77 V(MipsFloat64RoundUp) \ 78 V(MipsFloat64RoundTiesEven) \ 79 V(MipsCvtSD) \ 80 V(MipsCvtDS) \ 81 V(MipsTruncWD) \ 82 V(MipsRoundWD) \ 83 V(MipsFloorWD) \ 84 V(MipsCeilWD) \ 85 V(MipsTruncWS) \ 86 V(MipsRoundWS) \ 87 V(MipsFloorWS) \ 88 V(MipsCeilWS) \ 89 V(MipsTruncUwD) \ 90 V(MipsTruncUwS) \ 91 V(MipsCvtDW) \ 92 V(MipsCvtDUw) \ 93 V(MipsCvtSW) \ 94 V(MipsCvtSUw) \ 95 V(MipsLb) \ 96 V(MipsLbu) \ 97 V(MipsSb) \ 98 V(MipsLh) \ 99 V(MipsLhu) \ 100 V(MipsSh) \ 101 V(MipsLw) \ 102 V(MipsSw) \ 103 V(MipsLwc1) \ 104 V(MipsSwc1) \ 105 V(MipsLdc1) \ 106 V(MipsSdc1) \ 107 V(MipsFloat64ExtractLowWord32) \ 108 V(MipsFloat64ExtractHighWord32) \ 109 V(MipsFloat64InsertLowWord32) \ 110 V(MipsFloat64InsertHighWord32) \ 111 V(MipsFloat64SilenceNaN) \ 112 V(MipsFloat64Max) \ 113 V(MipsFloat64Min) \ 114 V(MipsFloat32Max) \ 115 V(MipsFloat32Min) \ 116 V(MipsPush) \ 117 V(MipsStoreToStackSlot) \ 118 V(MipsStackClaim) 119 120 // Addressing modes represent the "shape" of inputs to an instruction. 121 // Many instructions support multiple addressing modes. Addressing modes 122 // are encoded into the InstructionCode of the instruction and tell the 123 // code generator after register allocation which assembler method to call. 124 // 125 // We use the following local notation for addressing modes: 126 // 127 // R = register 128 // O = register or stack slot 129 // D = double register 130 // I = immediate (handle, external, int32) 131 // MRI = [register + immediate] 132 // MRR = [register + register] 133 // TODO(plind): Add the new r6 address modes. 134 #define TARGET_ADDRESSING_MODE_LIST(V) \ 135 V(MRI) /* [%r0 + K] */ \ 136 V(MRR) /* [%r0 + %r1] */ 137 138 139 } // namespace compiler 140 } // namespace internal 141 } // namespace v8 142 143 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 144