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1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 
8 namespace v8 {
9 namespace internal {
10 namespace compiler {
11 
12 // MIPS64-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V)  \
15   V(Mips64Add)                      \
16   V(Mips64Dadd)                     \
17   V(Mips64DaddOvf)                  \
18   V(Mips64Sub)                      \
19   V(Mips64Dsub)                     \
20   V(Mips64DsubOvf)                  \
21   V(Mips64Mul)                      \
22   V(Mips64MulHigh)                  \
23   V(Mips64DMulHigh)                 \
24   V(Mips64MulHighU)                 \
25   V(Mips64Dmul)                     \
26   V(Mips64Div)                      \
27   V(Mips64Ddiv)                     \
28   V(Mips64DivU)                     \
29   V(Mips64DdivU)                    \
30   V(Mips64Mod)                      \
31   V(Mips64Dmod)                     \
32   V(Mips64ModU)                     \
33   V(Mips64DmodU)                    \
34   V(Mips64And)                      \
35   V(Mips64Or)                       \
36   V(Mips64Nor)                      \
37   V(Mips64Xor)                      \
38   V(Mips64Clz)                      \
39   V(Mips64Lsa)                      \
40   V(Mips64Dlsa)                     \
41   V(Mips64Shl)                      \
42   V(Mips64Shr)                      \
43   V(Mips64Sar)                      \
44   V(Mips64Ext)                      \
45   V(Mips64Ins)                      \
46   V(Mips64Dext)                     \
47   V(Mips64Dins)                     \
48   V(Mips64Dclz)                     \
49   V(Mips64Ctz)                      \
50   V(Mips64Dctz)                     \
51   V(Mips64Popcnt)                   \
52   V(Mips64Dpopcnt)                  \
53   V(Mips64Dshl)                     \
54   V(Mips64Dshr)                     \
55   V(Mips64Dsar)                     \
56   V(Mips64Ror)                      \
57   V(Mips64Dror)                     \
58   V(Mips64Mov)                      \
59   V(Mips64Tst)                      \
60   V(Mips64Cmp)                      \
61   V(Mips64CmpS)                     \
62   V(Mips64AddS)                     \
63   V(Mips64SubS)                     \
64   V(Mips64SubPreserveNanS)          \
65   V(Mips64MulS)                     \
66   V(Mips64DivS)                     \
67   V(Mips64ModS)                     \
68   V(Mips64AbsS)                     \
69   V(Mips64SqrtS)                    \
70   V(Mips64MaxS)                     \
71   V(Mips64MinS)                     \
72   V(Mips64CmpD)                     \
73   V(Mips64AddD)                     \
74   V(Mips64SubD)                     \
75   V(Mips64SubPreserveNanD)          \
76   V(Mips64MulD)                     \
77   V(Mips64DivD)                     \
78   V(Mips64ModD)                     \
79   V(Mips64AbsD)                     \
80   V(Mips64SqrtD)                    \
81   V(Mips64MaxD)                     \
82   V(Mips64MinD)                     \
83   V(Mips64Float64RoundDown)         \
84   V(Mips64Float64RoundTruncate)     \
85   V(Mips64Float64RoundUp)           \
86   V(Mips64Float64RoundTiesEven)     \
87   V(Mips64Float32RoundDown)         \
88   V(Mips64Float32RoundTruncate)     \
89   V(Mips64Float32RoundUp)           \
90   V(Mips64Float32RoundTiesEven)     \
91   V(Mips64CvtSD)                    \
92   V(Mips64CvtDS)                    \
93   V(Mips64TruncWD)                  \
94   V(Mips64RoundWD)                  \
95   V(Mips64FloorWD)                  \
96   V(Mips64CeilWD)                   \
97   V(Mips64TruncWS)                  \
98   V(Mips64RoundWS)                  \
99   V(Mips64FloorWS)                  \
100   V(Mips64CeilWS)                   \
101   V(Mips64TruncLS)                  \
102   V(Mips64TruncLD)                  \
103   V(Mips64TruncUwD)                 \
104   V(Mips64TruncUwS)                 \
105   V(Mips64TruncUlS)                 \
106   V(Mips64TruncUlD)                 \
107   V(Mips64CvtDW)                    \
108   V(Mips64CvtSL)                    \
109   V(Mips64CvtSW)                    \
110   V(Mips64CvtSUw)                   \
111   V(Mips64CvtSUl)                   \
112   V(Mips64CvtDL)                    \
113   V(Mips64CvtDUw)                   \
114   V(Mips64CvtDUl)                   \
115   V(Mips64Lb)                       \
116   V(Mips64Lbu)                      \
117   V(Mips64Sb)                       \
118   V(Mips64Lh)                       \
119   V(Mips64Lhu)                      \
120   V(Mips64Sh)                       \
121   V(Mips64Lw)                       \
122   V(Mips64Lwu)                      \
123   V(Mips64Sw)                       \
124   V(Mips64Ld)                       \
125   V(Mips64Sd)                       \
126   V(Mips64Lwc1)                     \
127   V(Mips64Swc1)                     \
128   V(Mips64Ldc1)                     \
129   V(Mips64Sdc1)                     \
130   V(Mips64BitcastDL)                \
131   V(Mips64BitcastLD)                \
132   V(Mips64Float64ExtractLowWord32)  \
133   V(Mips64Float64ExtractHighWord32) \
134   V(Mips64Float64InsertLowWord32)   \
135   V(Mips64Float64InsertHighWord32)  \
136   V(Mips64Float64Max)               \
137   V(Mips64Float64Min)               \
138   V(Mips64Float64SilenceNaN)        \
139   V(Mips64Float32Max)               \
140   V(Mips64Float32Min)               \
141   V(Mips64Push)                     \
142   V(Mips64StoreToStackSlot)         \
143   V(Mips64StackClaim)
144 
145 // Addressing modes represent the "shape" of inputs to an instruction.
146 // Many instructions support multiple addressing modes. Addressing modes
147 // are encoded into the InstructionCode of the instruction and tell the
148 // code generator after register allocation which assembler method to call.
149 //
150 // We use the following local notation for addressing modes:
151 //
152 // R = register
153 // O = register or stack slot
154 // D = double register
155 // I = immediate (handle, external, int32)
156 // MRI = [register + immediate]
157 // MRR = [register + register]
158 // TODO(plind): Add the new r6 address modes.
159 #define TARGET_ADDRESSING_MODE_LIST(V) \
160   V(MRI) /* [%r0 + K] */               \
161   V(MRR) /* [%r0 + %r1] */
162 
163 
164 }  // namespace compiler
165 }  // namespace internal
166 }  // namespace v8
167 
168 #endif  // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
169