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Searched refs:FpuRegister (Results 1 – 10 of 10) sorted by relevance

/art/compiler/utils/mips64/
Dassembler_mips64.h233 void Bc1eqz(FpuRegister ft, uint16_t imm16);
234 void Bc1nez(FpuRegister ft, uint16_t imm16);
236 void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
237 void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
238 void MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
239 void DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
240 void AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
241 void SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
242 void MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
243 void DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
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Dassembler_mips64.cc156 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, in EmitFR()
170 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) { in EmitFI()
626 void Mips64Assembler::Bc1eqz(FpuRegister ft, uint16_t imm16) { in Bc1eqz()
630 void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) { in Bc1nez()
689 Bc1eqz(static_cast<FpuRegister>(rs), imm16_21); in EmitBcondc()
693 Bc1nez(static_cast<FpuRegister>(rs), imm16_21); in EmitBcondc()
701 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in AddS()
705 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SubS()
709 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MulS()
713 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in DivS()
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Dmanaged_register_mips64.h47 FpuRegister AsFpuRegister() const { in AsFpuRegister()
49 return static_cast<FpuRegister>(id_ - kNumberOfGpuRegIds); in AsFpuRegister()
75 static Mips64ManagedRegister FromFpuRegister(FpuRegister r) { in FromFpuRegister()
Dassembler_mips64_test.cc39 mips64::FpuRegister,
44 mips64::FpuRegister,
147 fp_registers_.push_back(new mips64::FpuRegister(mips64::F0)); in SetUpHelpers()
148 fp_registers_.push_back(new mips64::FpuRegister(mips64::F1)); in SetUpHelpers()
149 fp_registers_.push_back(new mips64::FpuRegister(mips64::F2)); in SetUpHelpers()
150 fp_registers_.push_back(new mips64::FpuRegister(mips64::F3)); in SetUpHelpers()
151 fp_registers_.push_back(new mips64::FpuRegister(mips64::F4)); in SetUpHelpers()
152 fp_registers_.push_back(new mips64::FpuRegister(mips64::F5)); in SetUpHelpers()
153 fp_registers_.push_back(new mips64::FpuRegister(mips64::F6)); in SetUpHelpers()
154 fp_registers_.push_back(new mips64::FpuRegister(mips64::F7)); in SetUpHelpers()
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/art/runtime/arch/mips64/
Dregisters_mips64.h71 enum FpuRegister { enum
108 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs);
Dregisters_mips64.cc40 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs) { in operator <<()
/art/compiler/optimizing/
Dcode_generator_mips64.cc514 static dwarf::Reg DWARFReg(FpuRegister reg) { in DWARFReg()
562 FpuRegister reg = kFpuCalleeSaves[i]; in GenerateFrameEntry()
599 FpuRegister reg = kFpuCalleeSaves[i]; in GenerateFrameExit()
668 destination.AsFpuRegister<FpuRegister>(), in MoveLocation()
700 __ Mtc1(gpr, destination.AsFpuRegister<FpuRegister>()); in MoveLocation()
702 __ Dmtc1(gpr, destination.AsFpuRegister<FpuRegister>()); in MoveLocation()
711 __ Dmtc1(source.AsRegister<GpuRegister>(), destination.AsFpuRegister<FpuRegister>()); in MoveLocation()
713 __ Mtc1(source.AsRegister<GpuRegister>(), destination.AsFpuRegister<FpuRegister>()); in MoveLocation()
720 __ MovS(destination.AsFpuRegister<FpuRegister>(), source.AsFpuRegister<FpuRegister>()); in MoveLocation()
723 __ MovD(destination.AsFpuRegister<FpuRegister>(), source.AsFpuRegister<FpuRegister>()); in MoveLocation()
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Dintrinsics_mips64.cc64 FpuRegister trg_reg = trg.AsFpuRegister<FpuRegister>(); in MoveFromReturnRegister()
150 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>(); in MoveFPToInt()
188 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>(); in MoveIntToFP()
389 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>(); in MathAbsFP()
390 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>(); in MathAbsFP()
462 FpuRegister a = locations->InAt(0).AsFpuRegister<FpuRegister>(); in GenMinMaxFP()
463 FpuRegister b = locations->InAt(1).AsFpuRegister<FpuRegister>(); in GenMinMaxFP()
464 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>(); in GenMinMaxFP()
468 FpuRegister ftmp = ((out != a) && (out != b)) ? out : FTMP; in GenMinMaxFP()
683 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>(); in VisitMathSqrt()
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Dcode_generator_mips64.h36 static constexpr FpuRegister kParameterFpuRegisters[] =
48 static constexpr FpuRegister kRuntimeParameterFpuRegisters[] =
56 static constexpr FpuRegister kFpuCalleeSaves[] =
62 class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
90 class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
/art/compiler/jni/quick/mips64/
Dcalling_convention_mips64.cc30 static const FpuRegister kFpuArgumentRegisters[] = {
105 FpuRegister arg = kFpuArgumentRegisters[reg_index]; in EntrySpills()